12.6.1 ACP requests

The read and write requests performed on the ACP behave differently depending on whether the request is coherent or not.

ACP requests behavior is as follows:

ACP coherent read requests

An ACP read request is coherent when ARUSERSC[0] = 0b1 and ARCACHESC[1] = 0b1, and ARVALIDSC is asserted.

In this case, the SCU enforces coherency.

When the data is present in one of the Cortex®‑R8 processor cores, the data is read directly from the relevant core, and returned to the ACP port.

When the data is not present in any of the cores, the read request is issued on one of the AXI3 master ports, with all its AXI parameters, except for the locked attribute.

ACP noncoherent read requests

An ACP read request is noncoherent when ARUSERSC[0] = 0b0 or ARCACHESC[1] = 0b0, and ARVALIDSC is asserted.

In this case, the SCU does not enforce coherency, and the read request is directly forwarded to one of the available AXI3 master ports.

ACP coherent write requests

An ACP write request is coherent when AWUSERSC[0] = 0b1 and AWCACHESC[1] = 0b1, and AWVALIDSC is asserted.

In this case, the SCU enforces coherency.

When the data is present in one of the Cortex‑R8 processor cores, the data is first cleaned and invalidated from the relevant core.

When the data is not present in any of the cores, or when it has been cleaned and invalidated, the write request is issued on one of the AXI3 master ports, along with all corresponding AXI3 parameters except for the locked attribute.

ACP noncoherent write requests

An ACP write request is noncoherent when AWUSERSC[0] = 0b1 or AWCACHESC[1] = 0b0, and AWVALIDSC is asserted.

In this case, the SCU does not enforce coherency, and the write request is forwarded directly to one of the available AXI3 master ports.

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