A.2 Clock and control signals

Details of the Cortex®‑R8 processor clock and control signals.

Table A-1 Clock and clock control signals

Name Type Source/destination Description
CLK Input Clock controller Global clock.
CPUCLKOFF[CN:0]a Input Reset controller

Individual core clock control, active-LOW:

0b0Clock is enabled.
0b1Clock is stopped.

This includes the FPU if it is present.

DBGCLKOFF[CN:0]a Input

Individual core debug clock control, active-LOW:

0b0Core debug clock is enabled.
0b1Core debug clock is stopped.
DUALPERIPHCLKb Input Clock controller Clock for dual SCU.
DUALPERIPHCLKENb Input Reset controller Clock enable for dual SCU and peripheral interface signals.
DUALPERIPHCLKOFFab Input Individual core clock control for timer, watchdog, and interrupt controller of dual SCU.
PERIPHCLK Input Clock controller Clock for the timer, watchdog, and interrupt controller.
PERIPHCLKEN Input Reset controller Clock enable for the timer, watchdog, and interrupt controller.
PERIPHCLKOFFab Input Individual core clock control for timer, watchdog, and interrupt controller of SCU.
SCUCLKOFFab Input Clock control delay for dual SCU.
CTCLKOFFa Input Used to control the CoreSight™ debug logic clock, that is, CTI0, CTI1, CTI2, CTI3, CTM, and ROM table.
ETM0CLKOFFa Input Controls the ETM0 clock, if ETM0 is present.
ETM1CLKOFFa Input Controls the ETM1 clock, if ETM1 is present.
ETM2CLKOFFa Input Controls the ETM2 clock, if ETM2 is present.
ETM3CLKOFFa Input Controls the ETM3 clock, if ETM3 is present.
Figure A-1 Clocking in lock-step or split/lock implementation
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a Deasserts the reset synchronously when leaving reset, but not used for clock enable.
b Only present if lock-step or split/lock is implemented. The figure shows how these signals are used in a lock-step or split/lock implementation.
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