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The Cortex®‑R8 processor core includes a Performance Monitoring Unit (PMU) that enables events, such as cache misses and instructions executed, to be counted over a period. The macrocell can still use these events by means of the extended external input facility. Each bit in the ETMEVENT[63:0] input is mapped to the corresponding extended external input.
Bits[3:0] of ETMEVENT are reserved for cross trigger connections. PMU event signals use bits[59:4], ECC signals use bits[61:60] if implemented, and the remainder are free for system- specific use if implemented. Any four of the external inputs can be selected for further use in the resource logic.
PMU event number 8, Executed instruction count, is presented by the core as a 6-bit vector which the ETM is not able to count. These are OR-gated together for connection to the ETM and the ETM is not able to count instruction execution directly.
The Cortex‑R8 processor core PMU can count two of the ETM external outputs as additional events. These events are not provided back to the macrocell as extended external inputs.
These facilities enable additional filtering of the system events using ETM resources, such as instruction address ranges or the start/stop resource, before they are passed back to the PMU for counting. To do this: