4.2.1 c0 registers

Summary of the 32-bit wide CP15 system control registers when CRn is c0.

Table 4-2 c0 register summary

Op1 CRm Op2 Name Reset Description
0 c0 0 MIDR 0x410FC181 4.3.1 Main ID Register
1 CTR 0x8333C003 Cache Type Registera
2 TCMTR Implementation dependentb TCM Type Registera
4 MPUIR Implementation dependentc 4.3.2 MPU Type Register
5 MPIDR Implementation dependentd 4.3.3 Multiprocessor Affinity Register
6 REVIDR Implementation dependent 4.3.4 Revision ID Register
c1 0 ID_PFR0 0x00000131 Processor Feature Register 0a
1 ID_PFR1 0x00000001 Processor Feature Register 1a
2 ID_DFR0 0x00010404 Debug Feature Registera
3 ID_AFR0 0x00000000 Auxiliary Feature Register 0a
4 ID_MMFR0 0x00110130 Memory Model Feature Register 0a
5 ID_MMFR1 0x00000000 Memory Model Feature Register 1a
6 ID_MMFR2 0x01200000 Memory Model Feature Register 2a
7 ID_MMFR3 0x00002111 Memory Model Feature Register 3a
c2 0 ID_ISAR0 0x02101111 Instruction Set Attributes Register 0a
1 ID_ISAR1 0x13112111 Instruction Set Attributes Register 1a
2 ID_ISAR2 0x21232141 Instruction Set Attributes Register 2a
3 ID_ISAR3 0x01112131 Instruction Set Attributes Register 3a
4 ID_ISAR4 0x00010142 Instruction Set Attributes Register 4a
1 c0 0 CCSIDR UNK 4.3.5 Cache Size ID Register
1 CLIDR Implementation dependente 4.3.6 Cache Level ID Register
7 AIDR 0x00000000 4.3.7 Auxiliary ID Register
2 c0 0 CSSELR Implementation dependent 4.3.8 Cache Size Selection Register
a  For information, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
b If TCMs are implemented 0x80010001. If TCMs are not implemented 0x00000000.
c For 12 MPU regions 0x00000c00. For 16 MPU regions 0x00001000. For 20 MPU regions 0x00001400. For 24 MPU regions 0x00001800.
d Dependent on external signal CLUSTERID and the number of configured cores in the Cortex®‑R8 processor.
e If cache present 0x09200003. If cache not present 0x00000000.
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