11.8.42 Power Down Status Register

The TRCPDSR indicates the powerdown status of the Cortex®‑R8 processor ETM.

Usage constraints
There are no usage constraints.
Available in all configurations.

Register number: 197

Base offset 0x314


Type: RO

Reset: 0x00000023

The following figure shows the TRCPDSR bit assignments.

Figure 11-51 TRCPDSR bit assignments
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The following table shows the TRCPDSR bit assignments.

Table 11-64 TRCPDSR bit assignments

Bits Name Function
[31:6] - Reserved. RAZ/WI.
[5] OSLK OS lock status.
[4:2] - Reserved. RAZ/WI.

Sticky powerdown state.

0b0Trace register power has not been removed since the TRCPDSR was last read.
0b1Trace register power has been removed since the TRCPDSR was last read.

This bit is set to 0b1 when power to the Cortex‑R8 processor ETM registers is removed, to indicate that programming state has been lost. It is cleared after a read of the TRCPDSR.


Indicates the Cortex‑R8 processor ETM is powered:

0b1 Cortex‑R8 processor ETM is powered. All registers are accessible.

If a system implementation allows the ETM to be powered off independently of the debug power domain, the system must handle accesses to the ETM appropriately.

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