11.8.59 Peripheral Identification Registers

The TRCPIDR0-7 provide the standard Peripheral ID required by all CoreSight™ components.

See the ARM® Embedded Trace Macrocell Architecture Specification ETMv4 for more information.

Usage constraints
Only bits[7:0] of each register are used. This means that TRCPIDR0-7 define a single 64-bit Peripheral ID, as the figure shows.
Configurations
Available in all configurations.
Attributes

Register number: 1012-1019

Base offset 0xFD0-0xFEC

Name: TRCPIDRn

Type: RO

Reset: -

The following figure shows the mapping between TRCPIDR0-7 and the single 64-bit Peripheral ID value.

Figure 11-69 Mapping between TRCPIDR0-7 and the Peripheral ID value
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The following figure shows the Peripheral ID bit assignments in the single conceptual Peripheral ID register.

Figure 11-70 Peripheral ID fields
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The following table shows the values of the fields when reading this set of registers. The ARM® Embedded Trace Macrocell Architecture Specification ETMv4 gives more information about many of these fields.

Table 11-82 TCRPIDR0-7 bit assignments

Register Register number Register offset Bits Value Description
TRCPIDR7 0x3F7 0xFDC [31:8] - Unused, read undefined.
    [7:0] 0x00 Reserved for future use, RAZ.
TRCPIDR6 0x3F6 0xFD8 [31:8] - Unused, read undefined.
    [7:0] 0x00 Reserved for future use, RAZ.
TRCPIDR5 0x3F5 0xFD4 [31:8] - Unused, read undefined.
    [7:0] 0x00 Reserved for future use, RAZ.
TRCPIDR4 0x3F4 0xFD0 [31:8] - Unused, read undefined.
    [7:4] 0x0 n, where 2n is number of 4KB blocks used.
    [3:0] 0x4 JEP 106 continuation code.
TRCPIDR3 0x3FB 0xFEC [31:8] - Unused, read undefined.
    [7:4] 0x0 RevAnd (at top level). Manufacturer revision number.
    [3:0] 0x0

Customer Modified.

0x0 indicates from ARM.

TRCPIDR2 0x3FA 0xFE8 [31:8] - Unused, read undefined.
    [7:4] a Revision Number of Peripheral. This value is the same as the Implementation revision field of the TRCIDR, see 11.8.31 ID Register 1.
    [3] 0b1 Always 1. Indicates that a JEDEC assigned value is used.
    [2:0] 0b011 JEP 106 identity code [6:4].
TRCPIDR1 0x3F9 0xFE4 [31:8] - Unused, read undefined.
    [7:4] 0b1011 JEP 106 identity code [3:0].
    [3:0] 0x9

Part Number[11:8].

Upper Binary Coded Decimal (BCD) value of Device Number.

TRCPIDR0 0x3F8 0xFE0 [31:8] - Unused, read undefined.
[7:0] 0x37

Part Number [7:0].

Middle and Lower BCD value of Device Number.

Note:

In the TCRPIDR0-7 bit assignments table, the 11.8.59 Peripheral Identification Registers are listed in order of register name, from most significant (TRCPIDR7) to least significant (TRCPIDR0). This does not match the order of the register offsets. Similarly, in the TRCCIDR0-3 bit assignments table the 11.8.60 Component Identification Registers are listed in order of register name, from most significant (TRCCIDR3) to least significant (TRCCIDR0).
a See the Description column for details.
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