11.8.49 Integration Mode Control Register

The TRCITCTRL enables topology detection or integration testing by putting the Cortex®‑R8 processor ETM into integration mode.

Usage constraints
ARM recommends that you perform a debug reset after using integration mode.
Available in all configurations.

Register number: 960

Base offset 0xF00


Type: RW

Reset: 0x00000000

The following figure shows the TRCITCTRL bit assignments.

Figure 11-59 TRCITCTRL bit assignments
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The following table shows the TRCITCTRL bit assignments.

Table 11-72 TRCITCTRL bit assignments

Bits Name Function
[31:1] - Reserved. RAZ/WI.
[0] IME

Integration mode enable:

0b0 Cortex‑R8 processor ETM is not in integration mode. This is the reset value.
0b1 Cortex‑R8 processor ETM is in integration mode.
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