12.6 Accelerator Coherency Port interface

The optional Accelerator Coherency Port (ACP) provides memory coherency between each core in the Cortex®‑R8 processor design and an external master.

The ACP is 64 bits wide, and conforms to the AMBA® 3 AXI standard as described in the ARM® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite.

This section contains the following subsections:
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