4.3.17 RAM Access Data Registers

RAM Access Data Registers (RADRLO and RADRHI) characteristics and bit assignments.

The RADRLO and RADRHI:

Read
Returns the 32-bit data value for the debug operation.
Write

Sets the value to be written by the direct RAM access operation.

Note:

Accesses to data cache use only RADRLO. RADRHI is RAZ/WI.

Accesses to instruction cache use both RADRLO and RADRHI because these accesses require 64-bit values.

Usage constraints

The RADRLO and RADRHI are only accessible in privileged mode.

Configurations
Available in all configurations.
Attributes
See the c15 register summary, 4.2.8 c15 registers.

The following figure shows the RADRLO bit assignments.

Figure 4-20 RADRLO bit assignments
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Note:

Bits [31:29] are 0b000 when the tag RAM is read. Only bits [28:0] are meaningful.

The following figure shows the RADRHI bit assignments.

Figure 4-21 RADRHI bit assignments
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To access the RADRLO, read or write the CP15 register with:

MRC p15, 0, <Rd>, c15, c1, 1 ; Read the CP15 debug cache/tcm access data register
MCR p15, 0, <Rd>, c15, c1, 1 ; Write the CP15 debug cache/tcm access data register

To access the RADRHI, read or write the CP15 register with:

MRC p15, 0, <Rd>, c15, c1, 2 ; Read the CP15 debug cache/tcm access data register
MCR p15, 0, <Rd>, c15, c1, 2 ; Write the CP15 debug cache/tcm access data register
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