A.5 Configuration signals

Details of the Cortex®‑R8 processor configuration signals.

Table A-4 Configuration signals

Name Type Source/destination Description
AXIPARITYLEVELa Input System configuration

Selects between odd and even parity for buses:

0b0Even parity.
0b1Odd parity.
CFGEND[CN:0] Input

Individual core endianness configuration.

Forces the EE bit in the CP15 c1 Control Register (SCTLR) to 1 at reset so that the core boots with big-endian data handling:

0b0EE bit is LOW.
0b1EE bit is HIGH.

This input is only sampled during reset of the core.

See 4.3.9 System Control Register.

CFGNMFI[CN:0] Input

Configuration of FIs to be nonmaskable:

0b0Clear the NMFI bit in the CP15 c1 Control Register.
0b1Set the NMFI bit in the CP15 c1 Control Register.

This input is only sampled during reset of the core.

See 4.3.9 System Control Register.

CLUSTERID[3:0] Input

Value read in Cluster ID field, bits[11:8], of the Multiprocessor Affinity Register (MPIDR).

See 4.3.3 Multiprocessor Affinity Register.

INITRAMx Input

Input present if TCM present for the corresponding core. It enables the core to boot from the Instruction TCM. This input, when tied HIGH, enables the instruction TCM on leaving reset.

See 4.3.14 ITCM Region Register.

MFILTEREN Input

For configurations with two master ports.

It enables filtering of address ranges at reset for AXI Master port 1. This signal is sampled on exit from reset and sets the default value of the MFILTEREN bit in the SCU Control Register. See 9.3.1 SCU Control Register.

0b0Address filtering off.
0b1Address filtering on.

See 9.3.1 SCU Control Register and 2.5.2 AXI master port 1.

MFILTEREND[11:0] Input

For configurations with two master ports.

Specifies the end address for address filtering at reset on AXI master port 1.

See 9.3.1 SCU Control Register and 2.5.2 AXI master port 1.

MFILTERSTART[11:0] Input System configuration

For configurations with two master ports.

Specifies the start address for address filtering at reset on AXI master port 1.

See 9.3.1 SCU Control Register and 2.5.2 AXI master port 1.

PERIPHBASE[31:13] Input

Specifies the base address for timers, watchdogs, interrupt controller, and SCU registers. Only accessible with memory-mapped accesses.

This value can be retrieved by a core using the Configuration Base Address Register. See 4.3.20 Configuration Base Address Register.

Note:

This address must be in the range defined by PFILTERSTART[11:0] and PFILTEREND[11:0].
PFILTEREND[11:0] Input

For configurations with the AXI low-latency peripheral port.

Specifies the end address for address filtering at reset on the AXI low-latency peripheral port.

See 2.5.3 AXI low-latency peripheral port.

PFILTERSTART[11:0] Input

For configurations with the AXI low-latency peripheral port.

Specifies the start address for address filtering at reset on the AXI low-latency peripheral port.

See 2.5.3 AXI low-latency peripheral port.

FPFILTERENDx[11:0] Input

For cores configured with an AXI fast peripheral port.

Specifies the end address for address filtering at reset on the AXI fast peripheral port.

See 2.5.4 AXI Fast Peripheral Port.

FPFILTERSTARTx[11:0] Input

For cores configured with an AXI fast peripheral port.

Specifies the start address for address filtering at reset on the AXI fast peripheral port.

See 2.5.4 AXI Fast Peripheral Port.

SMPnAMP[CN:0] Output System integrity controller

Indicates AMP or SMP mode for each core:

0b0Asymmetric.
0b1Symmetric.

This output reflects the value of ACTLR.SMP.

See 4.3.10 Auxiliary Control Register.

TEINIT[CN:0] Input System configuration

Individual core out-of-reset default exception handling state:

0b0ARM®.
0b1Thumb®.

This input is only sampled during core reset. It sets the initial value of SCTLR.TE.

See 4.3.9 System Control Register.

VINITHI[CN:0] Input

Individual core control of the location of the exception vectors at reset:

0b0Exception vectors start at address 0x00000000.
0b1Exception vectors start at address 0xFFFF0000.b

This input is only sampled during core reset. It sets the initial value of SCTLR.V.

See 4.3.9 System Control Register and 4.3.14 ITCM Region Register.

a Only present if bus ECC is selected. This is a build option.
b HIVECS == 1 is deprecated in PMSAv7.
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