A.4 Interrupt controller signals

Details of the Cortex®‑R8 processor interrupt controller signals.

Table A-3 Interrupt controller signals

Name Type Source/destination Description
IRQS[m:0] Input Interrupt sources

Interrupt distributor interrupt lines.

m can be 31, 63,…, up to 479 in increments of 32. If there are no interrupt lines, this input is removed.

nFIQ[CN:0] Input

Individual core legacy FIQ request input lines. Active-LOW interrupt request:

0b0Active interrupt.
0b1Do not activate interrupt.

The core treats the nFIQ input as level sensitive. The nFIQ input must be asserted until the core acknowledges the interrupt.

nFIQOUT[CN:0] Output Power controller Active-LOW FIQ outputs from the internal GIC to the appropriate core. These indicate when interrupts are being forwarded to the core.
nIRQ[CN:0] Input Interrupt sources

Individual core legacy IRQ request input lines. Active-LOW interrupt request:

0b0Active interrupt.
0b1Do not activate interrupt.

The core treats the nIRQ input as level sensitive. The nIRQ input must be asserted until the core acknowledges the interrupt.

nIRQOUT[CN:0] Output Power controller Active-LOW IRQ outputs from the internal GIC to the appropriate core. These indicate when interrupts are being forwarded to the core.
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