A.7 Power management signals

Details of the Cortex®‑R8 processor power management signals.

Table A-7 Power management signals

Name Type Source/destination Description
PWRCTLO0[1:0] Output Power controller Reset value for core 0 status field, bits[1:0] of SCU CPU Power Status Register.
PWRCTLO1[1:0]a Output Reset value for core 1 status field, bits[9:8] of SCU CPU Power Status Register.
PWRCTLO2[1:0]a Output Reset value for core 2 status field, bits[17:16] of SCU CPU Power Status Register.
PWRCTLO3[1:0]a Output Reset value for core 3 status field, bits[25:24] of SCU CPU Power Status Register.
SCUIDLE Output L2C-310 or power controller

In the case of the L2C-310, the SCUIDLE output can be connected to the STOPCLK input of the L2C-310. Indicates the SCU is idle.

The SCU is idle when all cores are in WFI or in powerdown, and there is no pending transaction in the SCU on any of the AXI ports, that is, ACP, AXI master 0, AXI master 1, or AXI low-latency peripheral port.

Note:

When using the ACP, even if there is no activity on the bus, the ACLKENSC input must remain HIGH, or must toggle at least once through HIGH, after the activity has stopped. If not, the SCUIDLE output cannot go HIGH.

a Only present if core 1-3 is present.
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