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The AXI slave Accelerator Coherency Port (ACP) is optional, and has optional ECC protection on data and parity on control bits. The ACP is an AXI3 64-bit slave port that can be connected to noncached AXI3 master peripherals, such as a DMA engine or cryptographic engine.
The following table shows the AXI Accelerator Coherency Port attributes.
Table 2-11 AXI slave Accelerator Coherency Port attributes
|Write acceptance capability||
17 non-shared or 5 shared (without ACP bridge)
18 non-shared or 6 shared (with ACP bridge)
|Read acceptance capability||
17 non-shared or shared (without ACP bridge)
18 non-shared or shared (with ACP bridge)
This AMBA3 AXI-compatible slave interface on the SCU provides an interconnect point for a range of system masters that, for overall system performance, power consumption, or to simplify software, are better interfaced directly with the Cortex®‑R8 processor.