11.8.27 Counter Value Registers 0-1

The TRCCNTVRn contain the current counter value.

Usage constraints
  • Can only be written when the Cortex®‑R8 processor ETM is disabled.
  • Must be programmed with an initial value when programming the counter.
Configurations
Available in all configurations.
Attributes

Register number: 88-89

Base offset 0x160-0x164

Name: TRCCNTVRn

Type: RW

Reset: -

The following figure shows the TRCCNTVRn bit assignments.

Figure 11-31 TRCCNTVRn bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the TRCCNTVRn bit assignments.

Table 11-43 TRCCNTVRn bit assignments

Bits Value Function
[31:16] - Reserved. RAZ/WI
[15:0] VALUE Contains the current counter value
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.