9.3.13 ECC Fatal Error Register

The ECC Fatal Error Register provides a double-bit ECC fatal error signal that indicates data written out of the processor might be corrupted. The system can use this signal to disable writes to external memory.

Usage constraints
Writes to this register are enabled when the access bit for the core is set in the SCU Access Control Register, see 9.3.9 SCU Access Control Register.
Configurations
Available only in configurations where ECC is implemented.
Attributes

Offset from PERIPHBASE[31:13]: 0x7C

Reset value: 0x0

The following figure shows the ECC Fatal Error Register bit assignments.

Figure 9-16 ECC Fatal Error Register bit assignments
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Table 9-17 ECC Fatal Error Register bit assignments

Bits Name Function
[31:9] - Reserved. SBZ.
[8] ECC fatal error detected

Set only when any core has an ECC fatal error.

Reset by software.

This bit is exported externally by FATALERRDET.

[7:4] - Reserved. SBZ.
[3] ECC fatal error detected for core 3

Set only when core 3 has an ECC fatal error.

Reset by software.

[2] ECC fatal error detected for core 2

Set only when core 2 has an ECC fatal error.

Reset by software.

[1] ECC fatal error detected for core 1

Set only when core 1 has an ECC fatal error.

Reset by software.

[0] ECC fatal error detected for core 0

Set only when core 0 has an ECC fatal error.

Reset by software.

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