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On the external AXI buses, control bits are protected by parity, and data is protected by ECC bits.
This protection is available on the following bus interfaces:
When a parity error is detected on any control bits of the AXI transfer, no correction is done, but an event is reported to the external system.
When a correctable ECC error is detected on the data bits, the data is corrected. If the ECC error is not correctable, an error event is reported.