11.8.30 ID Register 0

The TRCIDR0 indicates the tracing capabilities of the Cortex®‑R8 processor ETM.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Register number: 120

Base offset 0x1E0

Name: TRCIDR0

Type: RO

Reset: 0xXX001EFF

The following figure shows the TRCIDR0 bit assignments.

Figure 11-39 TRCIDR0 bit assignments
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The following table shows the TRCIDR0 bit assignments.

Table 11-51 TRCIDR0 bit assignments

Bits Name Function
[31:30] - Reserved. RAZ/WI.
[29] COMMOPT

Indicates the meaning of the commit field in some packets:

0b0Commit mode 0.
[28:24] TSSIZE

Global timestamp size. Driven from external TSSIZE pin:

0b00110Maximum of 48-bit global timestamp implemented. TSSIZE is LOW.
0b01000Maximum of 64-bit global timestamp implemented. TSSIZE is HIGH.

Other values are Reserved.

[23:17] - Reserved. RAZ/WI.
[16:15] QSUPP

Indicates Q element support:

0b00Q elements not supported.
[14] QFILT

Indicates Q element filtering support:

0b0Q element filtering not supported.
[13:12] CONDTYPE

Indicates how conditional results are traced:

0b01Full CPSR traced.
[11:10] NUMEVENT

Number of events supported in the trace, minus 1:

0b11
Four events supported.
[9] RETSTACK

Return stack support:

0b1
Return stack implemented.
[8] - Reserved. RAZ/WI.
[7] TRCCCI

Support for cycle counting in the instruction trace:

0b1Cycle counting in the instruction trace is implemented.
[6] TRCCOND

Support for conditional instruction tracing:

0b1Conditional instruction tracing is implemented.
[5] TRCBB

Support for branch broadcast tracing:

0b1Branch broadcast tracing is implemented.
[4:3] TRCDATA

Support for tracing of data:

0b11Tracing of data addresses and data values is implemented.
[2:1] INSTP0

Support for tracing of load and store instructions as P0 elements:

0b11Tracing of load and store instructions as P0 elements is implemented.
[0] - Reserved. RAO/WI.
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