4.2.14 Performance monitor registers

Summary of the performance monitor registers.

The following table shows the performance monitor registers.

Table 4-15 Performance monitor registers

Name CRn Op1 CRm Op2 Reset Description
PMCR c9 0 c12 0 0x41184000 Performance Monitor Control Registera
PMCNTENSET 1 0x00000000 Count Enable Set Registera
PMCNTENCLR 2 0x00000000 Count Enable Clear Registera
PMOVSR 3 0x00000000 Overflow Flag Status Registera
PMSWINC 4 UNK Software Increment Registera
PMSELR 5 0x00000000 Event Counter Selection Registera
PMCCNTR c13 0 UNK Cycle Count Registera
PMXEVTYPER 1 UNK Event Selection Registera
PMXEVCNTR c13 2 UNK Performance Monitor Count Registersa
PMUSERENR c14 0 0x00000000 User Enable Registera
PMINTENSET 1 0x00000000 Interrupt Enable Set Registera
PMINTENCLR 2 0x00000000 Interrupt Enable Clear Registera
a For information, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
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