11.8.25 Counter Control Register 0

The TRCCNTCTLR0 controls the counter.

Usage constraints
Can only be written when the Cortex®‑R8 processor ETM is disabled.
Configurations
Available in all configurations.
Attributes

Register number: 84

Base offset 0x150

Name: TRCCNTCTLR0

Type: RW

Reset: -

The following figure shows the TRCCNTCTLR0 bit assignments.

Figure 11-29 TRCCNTCTLR0 bit assignments
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The following table shows the TRCCNTCTLR0 bit assignments.

Table 11-41 TRCCNTCTLR0 bit assignments

Bits Name Function
[31:17] - Reserved. RAZ/WI.
[16] RLDSELF

Defines whether the counter reloads when it reaches zero:

0b0The counter does not reload when it reaches zero. The counter only reloads based on RLDTYPE and RLDSEL.
0b1The counter reloads when it reaches zero and the resource selected by CNTTYPE and CNTSEL is also active. The counter also reloads based on RLDTYPE and RLDSEL.
[15] RLDTYPE

Selects the resource type for the reload:

0b0Single selected resource.
0b1Boolean combined resource pair.
[14:12] - Reserved. RAZ/WI.
[11:8] RLDSEL

Selects the resource number, based on the value of RLDTYPE:

When RLDTYPE is 0b0, selects a single selected resource from 0-15 defined by bits[3:0].

When RLDTYPE is 0b1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

[7] CNTTYPE

Selects the resource type for the counter:

0b0Single selected resource.
0b1Boolean combined resource pair.
[6:4] - Reserved. RAZ/WI.
[3:0] CNTSEL

Selects the resource number, based on the value of CNTTYPE:

When CNTTYPE is 0b0, selects a single selected resource from 0-15 defined by bits[3:0].

When CNTTYPE is 0b1, selects a Boolean combined resource pair from 0-7 defined by bits[2:0].

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