1.5 Configurable options

List of features of the Cortex®‑R8 processor that can be configured using either build or pin configurations. Many of these features, if included, can also be enabled and disabled during software configuration.

Table 1-1 Configurable options

Feature Range of options Sub-options Build or pin configuration
Number of cores One to four - Build
Single core with optional redundancy Single core, no redundancy One processing core Build
Single core with redundancy Two cores, one built for lock-step mode Build
Dual core with optional redundancy Dual core, no redundancy Two processing cores Build
Dual core with redundancy Two cores, one built for lock-step mode Build and pin
Two processing cores Build and pin
Three cores Three cores, no redundancy Three processing cores Build
Four cores Four cores, no redundancy Four processing cores Build
Instruction cache No instruction cachea - Build
Instruction cache included

No ECCb

64-bit ECC

Build
4KB, 8KB, 16KB, 32KB, or 64KB Build
Data cache No data cachec - Build
Data cache included

No ECCb

32-bit ECC

Build
4KB, 8KB, 16KB, 32KB, or 64KB Build
Instruction TCM No Instruction TCM - Build
Instruction TCM included

No ECCb

64-bit ECC

Build
4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, or 1024KB Build
Data TCM No Data TCM - Build
Data TCM included

No ECCb

32-bit ECC

Build
4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, or 1024KB Build
Branch Target Address Cache (BTAC) size 512 entries -b Build
PREDictor (PRED) RAM size 4096 entries -b Build
FPU Not included - Build
Included Single-precision implementation Build
Double-precision implementation Build
MPU Number of regions 12 region option Build
16 region option Build
20 region option Build
24 region option Build
AXI master ports One port or two ports Port 0 Build
Port 1, with address filtering Build and pin
AXI low-latency peripheral port Not included - Build
Included - Build and pin
AXI fast peripheral port Not included - Build
Included One per core Build and pin
ETM Not included - Build
Included One per core Build
One shared with all cores Build
Memory Reconstruction Port (MRP) Included or not - Build
Support for ECC Used or not - Build
Number of interrupts 0-480 in range of 32 - Build
a If you select no instruction cache, you must also select no data cache.
b The ECC parameter is global for the instruction and data cache RAMs, and ITCM and DTCM. BTAC and PRED RAM are protected by parity, initiated using the same ECC parameter.
c If you select no data cache, you must also select no instruction cache.
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.