10.2 Memory Reconstruction Port

The MRP is an optional feature for the Cortex®‑R8 processor. All write accesses, regardless of memory attributes, such as Strongly Ordered, Device, Non-Cacheable, and cacheable, are exported from the core through this port so that an image of the memory can be reconstructed. This port is intended for memory reconstruction only.

The MRP can be enabled using the Auxiliary Control Register.

The MRP has the following restrictions:

  • Exclusive write accesses are reported on this interface only if they are successful. Failed exclusive write accesses never appear on this interface because they are never executed.
  • Because TCM accesses are not mapped externally, they are not reported on this interface.
  • When SWP accesses are atomic, the write access part of the SWP is exported on the interface when completed.
  • One interface is provided per core in a multiprocessor configuration. The implementer is responsible for synchronizing the different paths, if required, to be able to reconstruct an image of the memory.
  • Write accesses are not in program order, apart from any architectural constraints on the memory attributes. If you require the accesses to be visible in order on the MRP:

    • Use Device or Strongly-Ordered memory attributes.

    • Execute a Data Synchronization Barrier (DSB).

See A.16 Memory reconstruction port signals for a complete list of the MRP interface signals.

The ready signal of the SoC slave is used to drive the ready signal of the store buffer towards the LSU. As a result, asserting this signal LOW directly impacts the performance of the core, and writes are kept in the LSU until the SoC can execute the incoming writes. You can use a FIFO to provide limited and reasonable back-pressure on the ready signal.

Note:

There is no response channel on the MRP. Any possible dec/slave error is reported by the normal AXI channel.
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