9.3.9 SCU Access Control Register

The SCU Access Control Register controls access to SCU registers on a per core basis.

The SCU Access Control Register controls access to the following registers:

  • SCU Control Register.
  • SCU CPU Power Status Register.
  • SCU Invalidate All Register.
  • SCU Error Bank First Entry Register.
  • SCU Error Bank Second Entry Register.

The following figure shows the SCU Access Control Register bit assignments.

Figure 9-10 SCU Access Control Register bit assignments
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The following table shows the SCU Access Control Register bit assignments.

Table 9-11 SCU Access Control Register bit assignments

Bits Name Description
[31:4]   Reserved. SBZ.
[3] Core 3 SCU register access
0b1Core 3 can access the SCU registers. This is the default.
0b0Core 3 cannot access the SCU registers.
[2] Core 2 SCU register access
0b1Core 2 can access the SCU registers. This is the default.
0b0Core 2 cannot access the SCU registers.
[1] Core 1 SCU register access
0b1Core 1 can access the SCU registers. This is the default.
0b0Core 1 cannot access the SCU registers.
[0] Core 0 SCU register access
0b1Core 0 can access the SCU registers. This is the default.
0b0Core 0 cannot access the SCU registers.
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