11.8.24 Counter Reload Value Registers 0-1

The TRCCNTRLDVRn define the reload value for the counter.

Usage constraints
Can only be written when the Cortex®‑R8 processor ETM is disabled.
Available in all configurations.

Register number: 80-81

Base offset 0x140-0x144


Type: RW

Reset: -

The following figure shows the TRCCNTRLDVRn bit assignments.

Figure 11-28 TRCCNTRLDVRn bit assignments
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The following table shows the TRCCNTRLDVRn bit assignments.

Table 11-40 TRCCNTRLDVRn bit assignments

Bits Value Function
[31:16] - Reserved. RAZ/WI.
[15:0] VALUE Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs.
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