11.8.60 Component Identification Registers

The TRCCIDR0-3 identify the ETM as a CoreSight™ component.

For more information, see the ARM® Embedded Trace Macrocell Architecture Specification ETMv4.

Usage constraints
Only bits[7:0] of each register are used. This means that TRCCIDR0-3 define a single 32-bit Component ID, as the figure shows.
Configurations
Available in all configurations.
Attributes

Register number: 1020-1023

Base offset xFF0-0xFFC

Name: TRCCIDRn

Type: RO

Reset: -

The following figure shows the mapping between TRCCIDR0-3 and the single 32-bit Component ID value.

Figure 11-71 Mapping between TRCCIDR0-3 and the Component ID value
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The following table shows the Component ID bit assignments in the single conceptual Component ID register.

Table 11-83 TRCCIDR0-3 bit assignments

Register Register number Register offset Bits Value Description
TRCCIDR3 0x3FF 0xFFC [31:8] - Unused, read undefined.
      [7:0] 0xB1 Component identifier, bits[31:24].
TRCCIDR2 0x3FE 0xFF8 [31:8] - Unused, read undefined.
      [7:0] 0x05 Component identifier, bits[23:16].
TRCCIDR1 0x3FD 0xFF4 [31:8] - Unused, read undefined.
      [7:4] 0x9 Component class (component identifier, bits[15:12]).
      [3:0] 0x0 Component identifier, bits[11:8].
TRCCIDR0 0x3FC 0xFF0 [31:8] - Unused, read undefined.
      [7:0] 0x0D Component identifier, bits[7:0].
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