11.8.34 ID Register 4

The TRCIDR4 indicates the resources available in the Cortex®‑R8 processor ETM.

Usage constraints
There are no usage constraints.
Available in all configurations.

Register number: 124

Base offset 0x1F0


Type: RO

Reset: 0x01270124

The following figure shows the TRCIDR4 bit assignments.

Figure 11-43 TRCIDR4 bit assignments
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The following table shows the TRCIDR4 bit assignments.

Table 11-55 TRCIDR4 bit assignments

Bits Name Function
[31:28] NUMVMIDC

Number of Virtual Machine ID (VMID) comparators implemented:

0b0000VMID comparators are not implemented.
[27:24] NUMCIDC

Number of Context ID comparators implemented:

0b0001One context ID comparator is implemented.
[23:20] NUMSSCC

Number of Single-Shot comparator controls implemented:

0b0010Two single-shot comparator controls are implemented.

Number of resource selection pairs implemented:

0b0111Eight resource selection pairs are implemented. The first is not counted.
[15:12] NUMPC

Number of Cortex‑R8 core comparator inputs implemented:

0b0000Core comparator inputs are not implemented.
[11:9] - Reserved. RAZ/WI.

Data address comparisons implemented:

0b1Data address comparisons are supported.
[7:4] NUMDVC

Number of data value comparators implemented:

0b0010Two data value comparators are implemented.

Number of address comparator pairs implemented:

0b0100Four address comparator pairs are implemented.
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