2.5.1 AXI master port 0

AXI master port 0 has optional ECC protection on data, and parity on control bits. It does not support AXI locked writes, that is, AWLOCKM0[1] is always 0b0.

This port supports five bits of AXI IDs, although AXI IDs can be larger if the ACP has more than four bits of ID. For example, if the ACP ID has four bits, there are five bits on the AXI master port. If the ACP ID has eight bits, there are nine bits on the AXI master port.

Note:

  • ID bit encoding is used to differentiate between different types of traffic happening in parallel. The encoding of the IDs is implementation specific.
  • You can use the AxUSER buses to identify the origin of the traffic, that is, the core number, or the ACP.
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