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AXI master port 0 has optional ECC protection on data, and parity on control bits. It does not support AXI locked writes, that is, AWLOCKM0 is always
This port supports five bits of AXI IDs, although AXI IDs can be larger if the ACP has more than four bits of ID. For example, if the ACP ID has four bits, there are five bits on the AXI master port. If the ACP ID has eight bits, there are nine bits on the AXI master port.