9.3.10 SCU Error Bank First Entry Register

The SCU Error Bank First Entry Register shows the first SCU error bank entry.

Usage constraints
There are no usage constraints.
Configurations
Available only in configurations where ECC is implemented.
Attributes

Offset from PERIPHBASE[31:13]: 0x60

Reset value: -

The following figure shows the SCU Error Bank First Entry Register bit assignments.

Figure 9-11 SCU Error Bank First Entry Register bit assignments
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The following table shows the SCU Error Bank First Entry Register bit assignments.

Table 9-12 SCU Error Bank First Entry Register bit assignments

Bits Name Function
[31:28] Ways for core3 Ways for core 3
[27:24] Ways for core2 Ways for core 2.
[23:20] Ways for core1 Ways for core 1.
[19:16] Ways for core0 Ways for core 0.
[15:2] - Reserved. SBZ.
[1:0] Status

Error status. The values are:

0b00No error.
0b01Error seen by SCU tag RAM, but not handled by core.
0b10Error seen by both SCU and core.
0b11Error is confirmed by software.
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