7.5.2 SCU registers used in ECC
The SCU is seen as a peripheral by the Cortex®‑R8 processor core(s), and has its own memory-mapped register file.
The following SCU registers are used in ECC:
- SCU Control Register
- Bits[15:12] of this register are used to enable
ECC checking on the AXI ports.
- SCU Error Bank Registers
- Bits[13:5] of these registers hold the SCU tag RAM
index, and bits[1:0] show the error status.
- Performance counters
- Events related to the SCU are reported to the PMU
of each core. The performance counters can be configured to monitor
several ECC-related metrics.
- SCU Debug Cache Registers
These registers provide information on various aspects
of ECC for the SCU:
- The SCU Debug Tag
RAM Operation Register shows the address and action for the SCU
tag RAM access.
- The SCU Debug Tag RAM Data Value Register and SCU
Debug Tag RAM ECC Chunk Register contain the data from the memory
selected by the SCU Debug Tag RAM Operation Register.