9.7.1 Coherent and noncoherent mode

The coherency between the ACP traffic and the L1 data cache of the cores is triggered when AxUSERSC[0] = 1 and AxCACHESC[1] = 1.

  • AxUSERSC[0] is the shared bit.
  • AxCACHESC[1] = 1 indicates it is an NC, WT, WB, or a WBWA memory region.
  • AxCACHESC[1] = 0 indicates it is a SO, or DV memory region. Using the AxCACHESC[1] bit prevents SO and DV memory regions from taking part in the coherency mechanism, that is, SCU lookups, on the ACP.

The x in the signal name represents either R for read or W for write.

Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.