4.2.8 c15 registers

Summary of the 32-bit wide CP15 system control registers when CRn is c15.

Table 4-9 c15 register summary

Op1 CRm Op2 Name Reset Description
0 c0 0 PCR 0x0 4.3.15 Power Control Register
c1 0 CTDOR UNK 4.3.16 Cache and TCM Debug Operation Register
1 RADRLO UNK 4.3.17 RAM Access Data Registers, bits[31:0]
2 RADRHI UNK 4.3.17 RAM Access Data Registers, bits[63:32]
3 RAECCRa UNK 4.3.18 RAM Access ECC Register
c2 0 D_ECC_ENTRY_0a UNK 4.3.19 ECC Error Registers
1 D_ECC_ENTRY_1a UNK
2 D_ECC_ENTRY_2a UNK
c3 0 I_ECC_ENTRY_0a UNK
1 I_ECC_ENTRY_1a UNK
2 I_ECC_ENTRY_2a UNK
c4 0 DTCM_ECC_ENTRYb UNK
c5 0 ITCM_ECC_ENTRYb UNK
4 c0 0 CBAR UNK 4.3.20 Configuration Base Address Register
a Only present if ECC is present, otherwise RAZ/WI.
b Only present if ECC and TCM are present, otherwise RAZ/WI.
Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.