4.3.9 System Control Register

System Control Register (SCTLR) characteristics and bit assignments.

The SCTLR provides control and configuration of:

  • Memory alignment and endianness.
  • Memory protection and fault behavior.
  • MPU and cache enables.
  • Interrupts and behavior of interrupt latency.
  • Location for exception vectors.
  • Program flow prediction.

The following figure shows the SCTLR bit assignments.

Figure 4-8 SCTLR bit assignments
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The following table shows the SCTLR bit assignments.

Table 4-25 SCTLR bit assignments

Bits Name Access Function
[31] - - Reserved. RAZ/SBZP.
[30] TE RW

Thumb® exception Enable:

0b0Exceptions including reset are handled in ARM® state.
0b1Exceptions including reset are handled in Thumb state.

The TEINIT signal defines the reset value.

[29:28] - - Reserved. RAZ/SBZP.
[27] NMFI RO

Nonmaskable FIQ support.

The bit cannot be configured by software.

The CFGNMFI signal defines the reset value.

[26] - - Reserved. RAZ/SBZP.
[25] EE RW

Exception Endianness. This bit determines how the E bit in the CPSR is set on an exception:

0b0CPSR E bit is set to 0b0 on an exception.
0b1CPSR E bit is set to 0b1 on an exception.

The CFGEND signal defines the reset value.

[24] - - Reserved. RAZ/WI.
[23:22] - - Reserved. RAO/SBOP.
[21] FI RW

Fast Interrupts configuration enable bit.

This bit can be used to reduce interrupt latency. The permitted values of this bit are:

0b0All performance features enabled. This is the reset value.
0b1Low interrupt latency configuration. Some performance features disabled.
[20] - - Reserved. RAZ/SBZP.
[19] DZ RW

Divide by Zero fault enable bit.

This bit controls whether an integer divide by zero causes an undefined Instruction exception:

0b0Divide by zero returns the result zero, and no exception is taken. This is the reset value.
0b1Attempting a divide by zero causes an undefined Instruction exception on the SDIV or UDIV instruction.
[18] - - Reserved. RAO/SBOP.
[17] BR RW

Background Region bit.

When the MPU is enabled this bit controls how an access that does not map to any MPU memory region is handled:

0b0Any access to an address that is not mapped to an MPU region generates a Background Fault memory abort. This is the reset value.
0b1

The default memory map is used as a background region:

  • A privileged access to an address that does not map to an MPU region takes the properties defined for that address in the default memory map.
  • An unprivileged access to an address that does not map to an MPU region generates a Background Fault memory abort.
[16] - - Reserved. RAO/SBOP.
[15] - - Reserved. RAZ/SBZP.
[14] - - Reserved. RAZ/WI.
[13] V RW

Vectors bit. This bit selects the base address of the exception vectors:

0b0

Normal exception vectors, base address 0x00000000.

0b1High exception vectors, Hivecs, base address 0xFFFF0000.

At reset, the value of this bit is taken from VINITHI.

[12] Ia -

Determines if instructions can be cached at any available cache level:

0b0
Instruction caching disabled at all levels. This is the reset value.
0b1
Instruction caching enabled.
[11] Z RW

Enables program flow prediction:

0b0Program flow prediction disabled. This is the reset value.
0b1Program flow prediction enabled.
[10] SW RW

Swap/Swap Byte (SWP/SWPB) enable bit:

0b0SWP and SWPB are undefined. This is the reset value.
0b1SWP and SWPB perform normally.
[9:7] - - Reserved. RAZ/SBZP.
[6:3] - - Reserved. RAO/SBOP.
[2] Ca RW

Determines if data can be cached at any available cache level:

0b0Data caching disabled at all levels. This is the reset value.
0b1Data caching enabled.
[1] A RW

Enables strict alignment of data to detect alignment faults in data accesses:

0b0Strict alignment fault checking disabled. This is the reset value.
0b1Strict alignment fault checking enabled.

Any unaligned access to Device or Strongly-Ordered memory generates an alignment fault and therefore does not cause any peripheral interface access. This means that the access examples given in this manual never show unaligned accesses to Device or Strongly-Ordered memory.

[0] M RW

Enables the MPU:

0b0MPU disabled. This is the reset value.
0b1MPU enabled.

Attempts to modify read-only bits are ignored.

To access the SCTLR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c1, c0, 0 ; Read SCTLR
MCR p15, 0, <Rd>, c1, c0, 0 ; Write SCTLR
a RW if caches implemented, RAZ/WI if no caches.
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