4.2.9 System identification, control, and configuration register

Summary of the system identification, control, and configuration registers.

Table 4-10 System identification, control, and configuration registers

Name CRn Op1 CRm Op2 Reset Description
MIDR c0 0 c0 0 0x410FC180 4.3.1 Main ID Register
CTR 1 0x8333C003 Cache Type Registera
TCMTR 2 Implementation dependentb TCM Type Registera
MPUIR 4 Implementation dependentc 4.3.2 MPU Type Register
MPIDR 5 Implementation dependentd 4.3.3 Multiprocessor Affinity Register
REVIDR 6 Implementation dependent 4.3.4 Revision ID Register
ID_PFR0 c1 0 0x00000131 Processor Feature Register 0a
ID_PFR1 1 0x00000001 Processor Feature Register 1a
ID_DFR0 2 0x00010404 Debug Feature Registera
ID_AFR0 3 0x00000000 Auxiliary Feature Register 0a
ID_MMFR0 4 0x00110130 Memory Model Feature Register 0a
ID_MMFR1 5 0x00000000 Memory Model Feature Register 1a
ID_MMFR2 6 0x01200000 Memory Model Feature Register 2a
ID_MMFR3 7 0x00002111 Memory Model Feature Register 3a
ID_ISAR0 c2 0 0x02101111 Instruction Set Attributes Register 0a
ID_ISAR1 1 0x13112111 Instruction Set Attributes Register 1a
ID_ISAR2 c0 0 c2 2 0x21232141 Instruction Set Attributes Register 2a
ID_ISAR3 3 0x01112131 Instruction Set Attributes Register 3a
ID_ISAR4 4 0x00010142 Instruction Set Attributes Register 4a
CCSIDR c0 1 c0 0 UNKe 4.3.5 Cache Size ID Register
CLIDR 1 Implementation dependentf 4.3.6 Cache Level ID Register
AIDR 7 0x00000000 4.3.7 Auxiliary ID Register
CSSELR 2 c0 0 Implementation dependent 4.3.8 Cache Size Selection Register
SCTLR c1 0 c0 0 - 4.3.9 System Control Register
ACTLR 1 0x00000000 4.3.10 Auxiliary Control Register
CPACR 2 0xC0000000 4.3.11 Coprocessor Access Control Register
a  For information, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
b If TCMs are implemented 0x80010001. If TCMs are not implemented 0x00000000.
c For 12 MPU regions 0x00000c00. For 16 MPU regions 0x00001000. For 20 MPU regions 0x00001400. For 24 MPU regions 0x00001800.
d Dependent on external signal CLUSTERID and the number of configured cores in the Cortex®‑R8 processor.
e Dependent on cache sizes and whether cache is on or off.
f If cache present 0x09200003. If cache not present 0x00000000.
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