B.3.1 Single load and store operation cycle timings

Details of cycle timing for single load and store operations. The result latency is the latency of the first loaded register.

Table B-2 Single load and store operation cycle timings

Instruction cycles AGU cycles Result latency
Fast forward cases Other cases

LDR, [reg]

LDR, [reg imm]

LDR, [reg reg]

LDR, [reg reg LSL #2]

LDR, [reg reg LSL #3]

1 2 3

LDR, [reg reg LSL reg]

LDR, [reg reg LSR reg]

LDR, [reg reg ASR reg]

LDR, [reg reg ROR reg]

LDR, [reg reg, RRX]

2 3 4

LDRB, [reg]

LDRB, [reg imm]

LDRB, [reg reg]

LDRB, [reg reg LSL #2]

LDRB, [reg reg LSL #3]

LDRH, [reg]

LDRH, [reg imm]

LDRH, [reg reg]

LDRH, [reg reg LSL #2]

LDRH, [reg reg LSL #3]

1 2 3

LDRB, [reg reg LSL reg]

LDRB, [reg reg ASR reg]

LDRB, [reg reg LSL reg]

LDRB, [reg reg ASR reg]

LDRH, [reg reg LSL reg]

LDRH, [reg reg ASR reg]

LDRH, [reg reg LSL reg]

LDRH, [reg reg ASR reg]

2 3 4
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