11.2.2 Instruction trace generator

The instruction trace generator block generates the trace packets that are a compressed form of the execution information provided by the Cortex®‑R8 processor trace generation. The trace packets are then passed to the FIFO.

Non-ConfidentialPDF file icon PDF versionARM 100400_0001_03_en
Copyright © 2015–2017 ARM Limited or its affiliates. All rights reserved.