A.1 About the signal descriptions

The tables in this appendix list the Cortex®‑R8 processor signals, with their direction, either input or output, and a high-level description.

Unless stated otherwise, the signals in this section have the following formats:

  • <signal name>[<value>:0] where [<value>:0] is the signal bit range, for example DBGROMADDR[31:12].
  • <signal name>[CN:0], where CN represents the number of configured cores minus one, for example DBGACK[CN:0], if the number of configured cores is 2, CN = 1.
  • <signal name>x, where x represents the core ID number, 0, 1, 2 or 3, for example FPFILTERSTARTx.
  • <signal name>x[<value>:0] where x represents the core ID number, 0, 1, 2 or 3 and [<value>:0] is the signal bit range, for example FPUFLAGSx[1:0].

There is no link between the number of cores in a design and the number of AXI master ports in a design. A single core design can have one or two AXI master ports.

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