5.3 Instruction throughput and latency

Complex instruction dependencies and memory system interactions make it impossible to describe the exact cycle timing for all instructions in all circumstances. However, the timing figures provided here are accurate in most cases. For precise timing, you must use a cycle-accurate model of your processor.

The definitions of throughput and latency are:

Throughput
Throughput is the number of cycles after issue that another instruction can begin execution.
Latency

Latency is the number of cycles after which the data is available for another operation. The forward latency, Fwd, is relevant for Read-After-Write (RAW) hazards. The writeback latency, Wbck, is relevant for Write-After-Write (WAW) hazards.

Latency values assume that the instruction has been issued and that the FPU pipeline or the Cortex®‑R8 processor pipeline are not stalled.

The following table shows:

  • The FPU instruction throughput and latency cycles for all operations except loads, stores, and system register accesses.
  • The old ARM® assembler mnemonics and the ARM Unified Assembler Language (UAL) mnemonics.

Table 5-1 FPU instruction throughput and latency cycles

Old ARM assembler mnemonic UAL Single-precision Double-precision
Throughput Latency Throughput Latency
Fwd Wbck Fwd Wbck

FADD

FSUB

FCVT

FSHTOD, FSHTOS

FSITOD, FSITOS

FTOSHD, FTOSHS

FTOSID, FTOSIS

FTOSL, FTOUH

FTOUI{Z}D, FTOUI{Z}S

FTOULD, FTOULS, FUHTOD, FUHTOS

FUITOD, FUITOS

FULTOD, FULTOS

VADD

VSUB

VCVT

1 4 4 1 4 4

FMUL

FNMUL

VMUL

VNMUL

1 4 4 2 6 6

FMAC

FNMAC

FMSC

FNMSC

VMLA

VMLS

VNMLS

VNMLA

1 7 7 2 9 9

FCPY

FABS

FNEG

FCONST

VMOV

VABS

VNEG

VMOV

1 1 2 1 1 2

FMRSa

FMRR(S/D)

FMRD(L/H)

VMOV

1

2

1

- 3 1 - 3

FMSRb

FM(S/D)RR

FMD(L/H)R

VMOV 1 1 2 1 1 2
FMSTAT VMRS 1 - 3 1 - 3
FDIV VDIV 10 15 15 20 25 25
FSQRT VSQRT 13 17 17 28 32 32

FCMP

FCMPE

FCMPZ

FCMPEZ

VCMP

VCMP{E}

VCMP{E}

VCMP{E}

1 1 4 1 1 4
-

FCVT(T/B)

.F16.F32

1 2 2 - - -
-

FCVT(T/B)

.F32.F16

1 - 4 - - -
a FPU to ARM.
b ARM to FPU.
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