A.11.3 Bus ECC error signals on AXI master ports

Details of the Bus ECC error signals on AXI master ports. These signals are only present if ECC is implemented. The x at the end of the signal name represents either 0 for AXI master port 0 or 1 for the optional AXI master port 1.

Table A-36 Bus ECC error signals on AXI master ports

Name Type Source/destination Description
AXICORRERRMx Output AXI master port Correctable error on DR channel of AXI master port.
AXIFATALERRMx[4:0] Output

Fatal error on AXI master port:

[4] fatal error on DR channel.

[3] fatal error on AR channel.

[2] fatal error on DB channel.

[1] fatal error on DW channel.

[0] fatal error on AW channel.

ARVALIDPTYMx Output Parity for address valid.
ARREADYPTYMx Input Parity for address ready.
ARADDRPTYMx[3:0] Output Parity for address.
ARCTLPTYMx[3:0] Output

Parity signals:

[0] parity for address ID.

[1] parity for burst length.

[2] parity for burst size, burst type, and lock type.

[3] parity for cache type and protection.

ARUSERPTYMx Output Parity for transfer attributes.
RVALIDPTYMx Input Parity for read valid.
RREADYPTYMx Output Parity for read ready.
RCTLPTYMx[1:0] Input

Parity signals:

[0] parity for read ID.

[1] parity for read response and read last.

RDATAERRCODEMx[7:0] Input ECC bits on data bus, when BUS_ECC build parameter is set.
AWVALIDPTYMx Output Parity for address valid.
AWREADYPTYMx Input Parity for address ready.
AWADDRPTYMx[3:0] Output Parity for address.
AWCTLPTYMx[3:0] Output

Parity signals:

[0] parity for address ID.

[1] parity for burst length.

[2] parity for burst size, burst type, and lock type.

[3] parity for cache type and protection.

AWUSERPTYMx Output Parity for transfer attributes.
WVALIDPTYMx Output Parity for write valid.
WREADYPTYMx Input Parity for write ready.
WCTLPTYMx[2:0] Output AXI master port

Parity signals:

[0] parity for write ID.

[1] parity for write strobes.

[2] parity for write last.

WUSERPTYMx Output Parity for transfer attributes.
WDATAERRCODEMx[7:0] Output ECC bits on data bus, when BUS_ECC build parameter is set.
BVALIDPTYMx Input Parity for response valid.
BREADYPTYMx Output Parity for response ready.
BCTLPTYMx[1:0] Input

Parity signals:

[0] parity for response ID.

[1] parity for write response.

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