4.2.5 c7 registers

Summary of the 32-bit wide CP15 system control registers when CRn is c7.

Table 4-6 c7 register summary

Op1 CRm Op2 Name Reseta Description
0 c0 4 NOP - No operationb
c1 0 ICIALLUIS - Invalidate all instruction caches to PoU Inner Shareableb,
6 BPIALLIS - Invalidate entire branch predictor array Inner Shareableb
c5 0 ICIALLU - Invalidate entire instruction cacheb
1 ICIMVAU - Invalidate instruction cache by VA to PoUb
4 CP15ISB - Instruction Synchronization Barrier operationb
6 BPIALL - Invalidate entire branch predictor arrayb
7 BPIMVA - Invalidate MVA from branch predictorsb
c6 1 DCIMVAC - Invalidate data cache line by VA to PoCb
2 DCISW - Invalidate data cache line by Set/Wayb
c10 1 DCCMVAC - Clean data cache line to PoC by VAb
2 DCCSW - Clean data cache line by Set/Wayb
4 CP15DSB - Data Synchronization Barrier operationb
5 CP15DMB - Data Memory Barrier operationb
0 c11 1 DCCMVAU - Clean data or unified cache line by VA to PoUb
c14 1 DCCIMVAC - Clean and invalidate data cache line by VA to PoCb
2 DCCISW - Clean and invalidate data cache line by Set/Wayb
a These registers do not have a reset value because they are write-only.
b For information, see the ARM® Architecture Reference Manual ARMv7‑A and ARMv7‑R edition.
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