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This optimization is available for Cortex®‑R8 processors only, and only if the L2C-310 Cache Controller is present in the design.
When this feature is enabled, coherent linefill requests are sent speculatively to the L2C-310 Cache Controller in parallel with the SCU tag look-up. If the tag look-up misses, the confirmed linefill is sent to the L2C-310 and gets RDATA earlier because the speculative request already initiated the data request. When filtering is enabled, only port 0 can receive speculative linefills.
To support this optimization in the Cortex‑R8 processor: