A.14.4 Debug APB interface signals

Details of the Debug APB interface signals.

Table A-50 Debug APB interface signals

Name Type Source/destination Description
PENABLEDBG Input CoreSight™ APB devices APB clock enable. Indicates a second and subsequent cycle of a transfer.
PRDATADBG[31:0] Output APB read data bus.
PSELDBG Input

Debug registers select:

0b0Debug registers not selected.
0b1Debug registers selected.
PSLVERRDBG Output

APB slave error signal:

0b0No transfer error.
0b1Transfer error.
PWRITEDBG Input APB read/write signal.
PADDRDBG[16:2] Input CoreSight APB devices

Programming address. Bits[16:12] have the following meaning:

0b00000ROM table.
0b10000Core 0 debug.
0b10001Core 0 PMU.
0b10010Core 1 debug, if core 1 is present, otherwise reserved.
0b10011Core 1 PMU, if core 1 is present, otherwise reserved.
0b10100Core 2 debug, if core 2 is present, otherwise reserved.
0b10101Core 2 PMU, if core 2 is present, otherwise reserved.
0b10110Core 3 debug, if core 3 is present, otherwise reserved.
0b10111Core 3 PMU, if core 3 is present, otherwise reserved.
0b11000CTI0.
0b11001CTI1, if core 1 is present, otherwise reserved.
0b11010CTI2, if core 2 is present, otherwise reserved.
0b11011CTI3, if core 3 is present, otherwise reserved.
0b11100ETM0.
0b11101ETM1, if ETM1 is present, otherwise reserved.
0b11110ETM2, if ETM2 is present, otherwise reserved.
0b11111ETM3, if ETM3 is present, otherwise reserved.
PADDRDBG31 Input

APB address bus bit[31]:

0b0Not an external debugger access.
0b1External debugger access.
PREADYDBG Output APB slave ready. An APB slave can assert PREADY to extend a transfer.
PWDATADBG[31:0] Input APB write data.
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