9.3.11 SCU Error Bank Second Entry Register

The SCU Error Bank Second Entry Register shows the second SCU error bank entry.

Usage constraints
There are no usage constraints.
Configurations
Available only in configurations where ECC is implemented.
Attributes

Offset from PERIPHBASE[31:13]: 0x64

Reset value: -

The following figure shows the SCU Error Bank Second Entry Register bit assignments.

Figure 9-12 SCU Error Bank Second Entry Register bit assignments
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The following table shows the SCU Error Bank Second Entry Register bit assignments.

Table 9-13 SCU Error Bank Second Entry Register bit assignments

Bits Name Function
[31:16] Ways Ways in the SCU tag RAM, four bits per core.
[15:14] - Reserved. SBZ.
[13:5] Index Index in the SCU tag RAM.
[4:2] - Reserved. SBZ.
[1:0] Status

Error status. The values are:

0b00No error.
0b01Error seen by SCU tag RAM, but not handled by core.
0b10Error seen by both SCU and core.
0b11Error is confirmed by software.
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