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Load and store instructions are classed as single load and store instructions such as LDR instructions, load and store multiple instructions such as
For load multiple and store multiple instructions, the number of registers in the register list usually determines the number of cycles required to execute a load or store instruction.
The Cortex®‑R8 processor has an optimized path from a load instruction to a subsequent data processing instruction, saving one cycle on the load-use penalty.
This path is used when the following conditions are met: