4.3.3 Multiprocessor Affinity Register

The MPIDR provides an additional processor identification mechanism for scheduling purposes in a multiprocessor system.

Usage constraints
The MPIDR is only accessible in privileged mode.
Available in all configurations. The value of the U bit, bit[30], indicates a multiprocessor or a uniprocessor configuration.
See the c0 register summary, 4.2.1 c0 registers.

The following figure shows the MPIDR bit assignments.

Figure 4-3 MPIDR bit assignments
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The following table shows the MPIDR bit assignments.

Table 4-20 MPIDR bit assignments

Bits Name Function
[31] - Indicates the register uses the new multiprocessor format. This is always 0b1.
[30] U bit

Multiprocessing Extensions:

0b0Indicates the Cortex®‑R8 processor is a multiprocessor configuration, meaning it has several cores.
[29:12] - Reserved. SBZ.
[11:8] Cluster ID Value read in CLUSTERID configuration inputs. It identifies a Cortex‑R8 processor in a system that has several Cortex‑R8 processors present.
[7:2] - Reserved. SBZ.
[1:0] CPU ID

Indicates the core number in the multiprocessor configuration:

0x00Core 0.
0x01Core 1.
0x10Core 2.
0x11Core 3.

To access the MPIDR, read the CP15 register with:

MRC p15,0,<Rd>,c0,c0,5 ; read Multiprocessor ID register
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