9.3.7 LLP Filtering Start Address Register

The LLP Filtering Start Address Register provides the filtering start address for the AXI low-latency peripheral port.

Usage constraints
This register is read-only. For the peripheral port region to operate, the filtering start address must be lower than the filtering end address.
Configurations
Available in all configurations.
Attributes

Offset from PERIPHBASE[31:13]: 0x48

Reset value: Defined by PFILTERSTART input.

The following figure shows the LLP Filtering Start Address Register bit assignments.

Figure 9-8 LLP Filtering Start Address Register bit assignments
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The following table shows the LLP Filtering Start Address Register bit assignments.

Table 9-9 LLP Filtering Start Address Register bit assignments

Bits Name Description
[31:20] Filtering start address

Filtering start address for the peripheral port.

The default value is the value of PFILTERSTART sampled on exit from reset. The value on the input gives the upper address bits with 1MB granularity.

[19:0]   Reserved. SBZ.

See 2.5.3 AXI low-latency peripheral port.

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