A.3 Reset signals

Details of the Cortex®‑R8 processor reset signals.

Table A-2 Reset signals

Name Type Source/destination Description
nCPURESET[CN:0] Input Reset controller Individual core resets.
nCPUHALT[CN:0] Input

Individual core input.

It can be asserted while the core is in reset to stop the core from fetching and executing instructions after coming out of reset. While the core is halted in this way, the TCMs can be preloaded with the appropriate data.

When it is deasserted, the core starts fetching instructions from the reset vector address in the normal way.

nDBGRESET[CN:0] Input Core debug logic resets.
nPERIPHRESET Input Timer and interrupt controller reset.
nSCURESET Input SCU global reset.
nCTRESET Input Reset for CoreSight™ debug logic, that is, CTI0, CTI1, CTI2, CTI3, CTM, and ROM table.
nETM0RESET Input Reset for ETM0, if present.
nETM1RESET Input Reset for ETM1, if present.
nETM2RESET Input Reset for ETM2, if present.
nETM3RESET Input Reset for ETM3, if present.
nWDRESET[CN:0] Input Core watchdog resets.
WDRESETREQ[CN:0] Output Core watchdog reset requests.

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