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The TRCSTALLCTLR enables the Cortex®‑R8 processor ETM to stall the Cortex‑R8 processor if the Cortex‑R8 processor ETM FIFO overflows.
Register number: 11
The following figure shows the TRCSTALLCTLR bit assignments.
The following table shows the TRCSTALLCTLR bit assignments.
Table 11-24 TRCSTALLCTLR bit assignments
Sets the priority of data trace components, enabling the Cortex‑R8 processor ETM to discard some data if the data trace buffer space is less than LEVEL:
Prioritize instruction trace if instruction trace buffer space is less than LEVEL:
Stall Cortex‑R8 processor based on data trace buffer space:
Stall Cortex‑R8 processor based on instruction trace buffer space:
Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow: