11.8.8 Stall Control Register

The TRCSTALLCTLR enables the Cortex®‑R8 processor ETM to stall the Cortex‑R8 processor if the Cortex‑R8 processor ETM FIFO overflows.

Usage constraints
There are no usage constraints.
Configurations
Available in all configurations.
Attributes

Register number: 11

Base offset 0x02C

Name: TRCSTALLCTLR

Type: RW

Reset: -

The following figure shows the TRCSTALLCTLR bit assignments.

Figure 11-12 TRCSTALLCTLR bit assignments
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The following table shows the TRCSTALLCTLR bit assignments.

Table 11-24 TRCSTALLCTLR bit assignments

Bits Name Function
[31:13] - Reserved. RAZ/WI.
[12:11] DATADISCARD

Sets the priority of data trace components, enabling the Cortex‑R8 processor ETM to discard some data if the data trace buffer space is less than LEVEL:

0b00Discard no data.
0b01Discard loaded data transfers.
0b10Discard stored data transfers.
0b11Discard both loaded and stored data transfers.
[10] INSTPRIORITY

Prioritize instruction trace if instruction trace buffer space is less than LEVEL:

0b0Do not prioritize instruction trace.
0b1Prioritize instruction trace.
[9] DSTALL

Stall Cortex‑R8 processor based on data trace buffer space:

0b0Do not stall processor.
0b1Stall processor if data trace buffer space is less than LEVEL.
[8] ISTALL

Stall Cortex‑R8 processor based on instruction trace buffer space:

0b0Do not stall processor.
0b1Stall processor if instruction trace buffer space is less than LEVEL.
[7:4] - Reserved. RAZ/WI.
[3:2] LEVEL

Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow:

0b00Lowest level, where zero invasion occurs.
0b11Highest level, where the most invasion occurs to reduce the risk of overflow.
[1:0] - Reserved. RAZ/WI.
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