A.15.1 Processor trace interface signals

Details of the processor trace interface signals.

Table A-51 Processor trace interface signals

Signal name Type Source/destination Description
ETMBUS[321:0] Input Processor Combined ETM interface channel
ETMIFVALID Input Core active, interface stable
ETMIFENx Output Power control for ETM processor trace interface
ETMBACK Output Configurable output to stall processor
DBGACK[CN:0] Input Core is in debug state
CPUACTIVE Input Core is not in WFI/WFE or other low-power state
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