ARM® Versatile™ Express Beetle IoT Evaluation Board V2M-Beetle Technical Reference Manual


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 Precautions
1.1.1 Ensuring safety
1.1.2 Preventing damage
1.2 About the V2M‑Beetle evaluation board
1.3 Layout of the V2M‑Beetle evaluation board
2 Hardware Description
2.1 Overview of the V2M‑Beetle evaluation board
2.2 Architecture of the Beetle test chip
2.3 Beetle test chip GPIO interface
2.4 Clocks
2.5 Resets
2.6 USB interface
2.7 SPI ADC interface
2.8 Interrupts
2.9 Cordio® BT4 Bluetooth Low‑Energy radio and antenna
2.10 V2M‑Beetle board and expansion shield power
2.11 Beetle test chip power management
2.11.1 Active state
2.11.2 Sleep state
2.11.3 Deep sleep state
2.11.4 Powerdown sleep state
2.12 Board peripherals
2.13 Debug and trace
3 Board Configuration and operating modes
3.1 Board configuration and programming
3.2 Operating modes
4 Programmers Model
4.1 About this programmers model
4.2 Memory map
4.3 Dual timer registers
4.4 UART registers
4.5 Watchdog registers
4.6 GPIO registers
4.7 System controller registers
4.7.1 System control register summary
4.7.2 PMUCTRL
4.7.3 RESETOP
4.7.4 RSTINFO
4.7.5 AHBPER0SET
4.7.6 AHBPER0CLR
4.7.7 APBPER0SET
4.7.8 APBPER0CLR
4.7.9 MAINCLK
4.7.10 AUXCLK
4.7.11 AHBCLKCFG0SET
4.7.12 AHBCLKCFG0CLR
4.7.13 AHBCLKCFG1SET
4.7.14 AHBCLKCFG1CLR
4.7.15 AHBCLKCFG2SET
4.7.16 AHBCLKCFG2CLR
4.7.17 APBCLKCFG0SET
4.7.18 APBCLKCFG0CLR
4.7.19 APBCLKCFG1SET
4.7.20 APBCLKCFG1CLR
4.7.21 APBCLKCFG2SET
4.7.22 APBCLKCFG2CLR
4.7.23 AHBPRST0SET
4.7.24 AHBPRST0CLR
4.7.25 APBPRST0SET
4.7.26 APBPRST0CLR
4.7.27 PWRDNCFG0SET
4.7.28 PWRDNCFG0CLR
4.7.29 PWRDNCFG1SET
4.7.30 PWRDNCFG1CLR
4.7.31 RTCRESET
4.7.32 EVENTCFG
4.7.33 PID4
4.7.34 PID5
4.7.35 PID6
4.7.36 PID7
4.7.37 PID0
4.7.38 PID1
4.7.39 PID2
4.7.40 PID3
4.7.41 CID0
4.7.42 CID1
4.7.43 CID2
4.7.44 CID3
A.1 Signal Descriptions
A.1.1 Expansion shield interface connectors
A.1.2 ICSP connector
A.1.3 USB connector
A.1.4 CoreSight™ 20 debug connector
A.1.5 CoreSight™ 10 debug connector
B.2 Specifications
B.2.1 Specifications
C.3 Revisions
C.3.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 01 June 2016 Non-Confidential First issue of Technical Reference Manual

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Confidentiality Status

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Product Status

The information in this document is Final, that is for a developed product.

Web Address

Conformance Notices

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling Versatile™ Express boards.
The motherboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:
  • Ensure attached cables do not lie across the target board
  • Reorient the receiving antenna
  • Increase the distance between the equipment and the receiver
  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
  • Consult the dealer or an experienced radio/TV technician for help

Note

It is recommended that wherever possible shielded interface cables are used.
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