Arm® Cortex®‑A65 Core Technical Reference Manual

Revision r1p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographic conventions
Timing diagrams
Signals
Additional reading
Feedback
Feedback on this product
Feedback on content
Part A Functional description
A1 Introduction
A1.1 About the core
A1.2 Features
A1.3 Implementation options
A1.4 Supported standards and specifications
A1.5 Test features
A1.6 Design tasks
A1.7 Product revisions
A2 Technical overview
A2.1 Components
A2.2 Interfaces
A2.3 About system control
A2.4 About the Generic Timer
A3 Clocks, resets, and input synchronization
A3.1 About clocks, resets, and input synchronization
A3.2 Asynchronous interface
A4 Power management
A4.1 About power management
A4.2 Voltage domains
A4.3 Power domains
A4.4 Architectural clock gating modes
A4.4.1 Core Wait for Interrupt
A4.4.2 Core Wait for Event
A4.5 Power control
A4.6 Core power modes
A4.6.1 On
A4.6.2 Off
A4.6.3 Off (emulated)
A4.6.4 SIMD dynamic retention
A4.6.5 Core dynamic retention
A4.6.6 Debug recovery
A4.6.7 Encoding for core power modes
A4.7 Thread power modes
A4.7.1 Run mode
A4.7.2 Standby mode
A4.7.3 Deactivated mode
A4.8 Relationship between power modes and power domains
A4.9 Power down sequence
A4.10 Debug over powerdown
A5 Memory Management Unit
A5.1 About the MMU
A5.1.1 Main functions
A5.1.2 AArch64 MMU behavior
A5.2 TLB organization
A5.2.1 L1 TLB
A5.2.2 L2 TLB
A5.2.3 IPA cache RAM
A5.2.4 Walk cache RAM
A5.3 TLB match process
A5.4 Translation table walks
A5.5 MMU memory accesses
A5.5.1 Configuring MMU accesses
A5.5.2 Hardware management of the Access flag and dirty state
A5.6 Responses
A5.6.1 MMU responses
A5.6.2 MMU aborts
A5.6.3 External aborts
A5.6.4 Mis-programming contiguous hints
A5.6.5 Conflict aborts
A5.6.6 Memory Behavior
A5.6.7 Support for Arm®v8‑A device memory types
A6 Level 1 memory system
A6.1 About the L1 memory system
A6.2 Cache behavior
A6.2.1 Instruction cache disabled behavior
A6.2.2 Instruction cache speculative memory accesses
A6.2.3 Data cache disabled behavior
A6.2.4 Data cache maintenance considerations
A6.2.5 Data cache coherency
A6.2.6 Write Streaming Mode
A6.2.7 Data cache invalidate on reset
A6.3 L1 instruction memory system
A6.3.1 Program flow prediction
A6.4 L1 data memory system
A6.4.1 Memory system implementation
A6.4.2 Internal exclusive monitor
A6.4.3 Exclusive monitor
A6.5 Data prefetching
A6.6 Direct access to internal memory
A6.6.1 Encoding for tag and data in the L1 data cache
A6.6.2 Encoding for tag and data in the L1 instruction cache
A6.6.3 Encoding for the L2 TLB
A6.6.4 Main TLB RAM descriptor fields
A6.6.5 Walk cache descriptor fields
A6.6.6 IPA cache descriptor fields
A7 Level 2 memory system
A7.1 About the L2 memory system
A7.2 Optional integrated L2 cache
A7.3 Support for memory types
A8 Reliability, Availability, and Serviceability (RAS)
A8.1 Cache ECC and parity
A8.2 Cache protection behavior
A8.3 Uncorrected errors and data poisoning
A8.4 RAS error types
A8.5 Error synchronization barrier
A8.6 Error recording
A8.7 Error injection
A9 Generic Interrupt Controller CPU interface
A9.1 About the Generic Interrupt Controller CPU interface
A9.2 Bypassing the CPU interface
A10 Advanced SIMD and floating-point support
A10.1 About the Advanced SIMD and floating-point support
A10.2 Accessing the feature identification registers
Part B Register descriptions
B1 AArch64 system registers
B1.1 AArch64 registers
B1.2 AArch64 architectural system register summary
B1.3 AArch64 IMPLEMENTATION DEFINED register summary
B1.4 AArch64 registers by functional group
B1.5 ACTLR_EL1, Auxiliary Control Register, EL1
B1.6 ACTLR_EL2, Auxiliary Control Register, EL2
B1.7 ACTLR_EL3, Auxiliary Control Register, EL3
B1.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1
B1.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2
B1.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
B1.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
B1.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2
B1.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3
B1.14 AIDR_EL1, Auxiliary ID Register, EL1
B1.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1
B1.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2
B1.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3
B1.18 CCSIDR_EL1, Cache Size ID Register, EL1
B1.19 CLIDR_EL1, Cache Level ID Register, EL1
B1.20 CPACR_EL1, Architectural Feature Access Control Register, EL1
B1.21 CPTR_EL2, Architectural Feature Trap Register, EL2
B1.22 CPTR_EL3, Architectural Feature Trap Register, EL3
B1.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1
B1.24 CPUCFR_EL1, CPU Configuration Register, EL1
B1.25 CPUECTLR_EL1, CPU Extended Control Register, EL1
B1.26 CPUPCR_EL3, CPU Private Control Register, EL3
B1.27 CPUPMR_EL3, CPU Private Mask Register, EL3
B1.28 CPUPOR_EL3, CPU Private Operation Register, EL3
B1.29 CPUPSELR_EL3, CPU Private Selection Register, EL3
B1.30 CPUPWRCTLR_EL1, Power Control Register, EL1
B1.31 CSSELR_EL1, Cache Size Selection Register, EL1
B1.32 CTR_EL0, Cache Type Register, EL0
B1.33 DCZID_EL0, Data Cache Zero ID Register, EL0
B1.34 DISR_EL1, Deferred Interrupt Status Register, EL1
B1.35 ERRIDR_EL1, Error ID Register, EL1
B1.36 ERRSELR_EL1, Error Record Select Register, EL1
B1.37 ERXCTLR_EL1, Selected Error Record Control Register, EL1
B1.38 ERXFR_EL1, Selected Error Record Feature Register, EL1
B1.39 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
B1.40 ERXPFGCDN_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
B1.41 ERXPFGCTL_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
B1.42 ERXPFGF_EL1, Selected Pseudo Fault Generation Feature Register, EL1
B1.43 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
B1.44 ESR_EL1, Exception Syndrome Register, EL1
B1.45 ESR_EL2, Exception Syndrome Register, EL2
B1.46 ESR_EL3, Exception Syndrome Register, EL3
B1.47 HACR_EL2, Hyp Auxiliary Configuration Register, EL2
B1.48 HCR_EL2, Hypervisor Configuration Register, EL2
B1.49 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0
B1.50 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1
B1.51 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1
B1.52 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1
B1.53 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
B1.54 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
B1.55 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1
B1.56 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1
B1.57 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
B1.58 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
B1.59 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
B1.60 LORC_EL1, LORegion Control Register, EL1
B1.61 LORID_EL1, LORegion ID Register, EL1
B1.62 LORN_EL1, LORegion Number Register, EL1
B1.63 MDCR_EL3, Monitor Debug Configuration Register, EL3
B1.64 MIDR_EL1, Main ID Register, EL1
B1.65 MPIDR_EL1, Multiprocessor Affinity Register, EL1
B1.66 PAR_EL1, Physical Address Register, EL1
B1.67 REVIDR_EL1, Revision ID Register, EL1
B1.68 RMR_EL3, Reset Management Register
B1.69 RVBAR_EL3, Reset Vector Base Address Register, EL3
B1.70 SCTLR_EL1, System Control Register, EL1
B1.71 SCTLR_EL2, System Control Register, EL2
B1.72 SCTLR_EL3, System Control Register, EL3
B1.73 TCR_EL1, Translation Control Register, EL1
B1.74 TCR_EL2, Translation Control Register, EL2
B1.75 TCR_EL3, Translation Control Register, EL3
B1.76 TTBR0_EL1, Translation Table Base Register 0, EL1
B1.77 TTBR0_EL2, Translation Table Base Register 0, EL2
B1.78 TTBR0_EL3, Translation Table Base Register 0, EL3
B1.79 TTBR1_EL1, Translation Table Base Register 1, EL1
B1.80 TTBR1_EL2, Translation Table Base Register 1, EL2
B1.81 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2
B1.81.1 VDISR_EL2 at EL1 using AArch64
B1.82 VSESR_EL2, Virtual SError Exception Syndrome Register
B1.83 VTCR_EL2, Virtualization Translation Control Register, EL2
B1.84 VTTBR_EL2, Virtualization Translation Table Base Register, EL2
B2 Error system registers
B2.1 Error system register summary
B2.2 ERR0CTLR, Error Record Control Register
B2.3 ERR0FR, Error Record Feature Register
B2.4 ERR0MISC0, Error Record Miscellaneous Register 0
B2.5 ERR0PFGCDN, Error Pseudo Fault Generation Count Down Register
B2.6 ERR0PFGCTL, Error Pseudo Fault Generation Control Register
B2.7 ERR0PFGF, Error Pseudo Fault Generation Feature Register
B2.8 ERR0STATUS, Error Record Primary Status Register
B3 GIC registers
B3.1 CPU interface registers
B3.2 AArch64 physical GIC CPU interface system register summary
B3.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1
B3.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1
B3.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1
B3.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1
B3.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
B3.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
B3.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
B3.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2
B3.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
B3.12 AArch64 virtual GIC CPU interface register summary
B3.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0, EL1
B3.14 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0, EL1
B3.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1
B3.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1
B3.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1
B3.18 AArch64 virtual interface control system register summary
B3.19 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2
B3.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2
B3.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
B3.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2
B3.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
B4 Advanced SIMD and floating-point registers
B4.1 AArch64 register summary
B4.2 FPCR, Floating-point Control Register
B4.3 FPSR, Floating-point Status Register
Part C Debug descriptions
C1 Debug
C1.1 About debug methods
C1.2 Debug functional description
C1.3 Debug register interfaces
C1.3.1 Core interfaces
C1.3.2 Breakpoints and watchpoints
C1.3.3 Effects of resets on debug registers
C1.3.4 External access permissions to debug registers
C1.4 Debug events
C1.4.1 Watchpoint debug events
C1.4.2 Debug OS Lock
C1.5 External debug interface
C2 Performance Monitor Unit
C2.1 About the PMU
C2.2 PMU functional description
C2.3 External register access permissions to the PMU registers
C2.4 PMU events
C2.5 PMU interrupts
C2.6 Exporting PMU events
C3 Embedded Trace Macrocell
C3.1 About the ETM
C3.2 ETM trace unit generation options and resources
C3.3 ETM trace unit functional description
C3.4 Resetting the ETM
C3.5 Programming and reading ETM trace unit registers
C3.6 ETM trace unit register interfaces
C3.7 Interaction with the PMU and Debug
Part D Debug registers
D1 AArch64 debug registers
D1.1 AArch64 debug register summary
D1.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
D1.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
D1.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
D1.5 MDSCR_EL1, Monitor Debug System Control Register, EL1
D2 Memory-mapped debug registers
D2.1 Memory-mapped debug register summary
D2.2 EDCIDR0, External Debug Component Identification Register 0
D2.3 EDCIDR1, External Debug Component Identification Register 1
D2.4 EDCIDR2, External Debug Component Identification Register 2
D2.5 EDCIDR3, External Debug Component Identification Register 3
D2.6 EDDEVID, External Debug Device ID Register 0
D2.7 EDDEVID1, External Debug Device ID Register 1
D2.8 EDDFR, External Debug Feature Register
D2.9 EDITCTRL, External Debug Integration Mode Control Register
D2.10 EDPFR, External Debug Processor Feature Register
D2.11 EDPIDR0, External Debug Peripheral Identification Register 0
D2.12 EDPIDR1, External Debug Peripheral Identification Register 1
D2.13 EDPIDR2, External Debug Peripheral Identification Register 2
D2.14 EDPIDR3, External Debug Peripheral Identification Register 3
D2.15 EDPIDR4, External Debug Peripheral Identification Register 4
D2.16 EDPIDRn, External Debug Peripheral Identification Registers 5-7
D2.17 EDRCR, External Debug Reserve Control Register
D3 AArch64 PMU registers
D3.1 AArch64 PMU register summary
D3.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
D3.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
D3.4 PMCR_EL0, Performance Monitors Control Register, EL0
D4 Memory-mapped PMU registers
D4.1 Memory-mapped PMU register summary
D4.2 PMCFGR, Performance Monitors Configuration Register
D4.3 PMCIDR0, Performance Monitors Component Identification Register 0
D4.4 PMCIDR1, Performance Monitors Component Identification Register 1
D4.5 PMCIDR2, Performance Monitors Component Identification Register 2
D4.6 PMCIDR3, Performance Monitors Component Identification Register 3
D4.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0
D4.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1
D4.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2
D4.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3
D4.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4
D4.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7
D5 PMU snapshot registers
D5.1 PMU snapshot register summary
D5.2 PMPCSSR, Snapshot Program Counter Sample Register
D5.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register
D5.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register
D5.5 PMSSSR, PMU Snapshot Status Register
D5.6 PMOVSSR, PMU Overflow Status Snapshot Register
D5.7 PMCCNTSR, PMU Cycle Counter Snapshot Register
D5.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5
D5.9 PMSSCR, PMU Snapshot Capture Register
D6 ETM registers
D6.1 ETM register summary
D6.2 TRCACATRn, Address Comparator Access Type Registers 0-7
D6.3 TRCACVRn, Address Comparator Value Registers 0-7
D6.4 TRCAUTHSTATUS, Authentication Status Register
D6.5 TRCAUXCTLR, Auxiliary Control Register
D6.6 TRCBBCTLR, Branch Broadcast Control Register
D6.7 TRCCCCTLR, Cycle Count Control Register
D6.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
D6.9 TRCCIDCVR0, Context ID Comparator Value Register 0
D6.10 TRCCIDR0, ETM Component Identification Register 0
D6.11 TRCCIDR1, ETM Component Identification Register 1
D6.12 TRCCIDR2, ETM Component Identification Register 2
D6.13 TRCCIDR3, ETM Component Identification Register 3
D6.14 TRCCLAIMCLR, Claim Tag Clear Register
D6.15 TRCCLAIMSET, Claim Tag Set Register
D6.16 TRCCNTCTLR0, Counter Control Register 0
D6.17 TRCCNTCTLR1, Counter Control Register 1
D6.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
D6.19 TRCCNTVRn, Counter Value Registers 0-1
D6.20 TRCCONFIGR, Trace Configuration Register
D6.21 TRCDEVAFF0, Device Affinity Register 0
D6.22 TRCDEVAFF1, Device Affinity Register 1
D6.23 TRCDEVARCH, Device Architecture Register
D6.24 TRCDEVID, Device ID Register
D6.25 TRCDEVTYPE, Device Type Register
D6.26 TRCEVENTCTL0R, Event Control 0 Register
D6.27 TRCEVENTCTL1R, Event Control 1 Register
D6.28 TRCEXTINSELR, External Input Select Register
D6.29 TRCIDR0, ID Register 0
D6.30 TRCIDR1, ID Register 1
D6.31 TRCIDR2, ID Register 2
D6.32 TRCIDR3, ID Register 3
D6.33 TRCIDR4, ID Register 4
D6.34 TRCIDR5, ID Register 5
D6.35 TRCIDR8, ID Register 8
D6.36 TRCIDR9, ID Register 9
D6.37 TRCIDR10, ID Register 10
D6.38 TRCIDR11, ID Register 11
D6.39 TRCIDR12, ID Register 12
D6.40 TRCIDR13, ID Register 13
D6.41 TRCIMSPEC0, Implementation Specific Register 0
D6.42 TRCITATBIDR, Integration ATB Identification Register
D6.43 TRCITCTRL, Integration Mode Control Register
D6.44 TRCITIATBINR, Integration Instruction ATB In Register
D6.45 TRCITIATBOUTR, Integration Instruction ATB Out Register
D6.46 TRCITIDATAR, Integration Instruction ATB Data Register
D6.47 TRCLAR, Software Lock Access Register
D6.48 TRCLSR, Software Lock Status Register
D6.49 TRCCNTVRn, Counter Value Registers 0-1
D6.50 TRCOSLAR, OS Lock Access Register
D6.51 TRCOSLSR, OS Lock Status Register
D6.52 TRCPDCR, Power Down Control Register
D6.53 TRCPDSR, Power Down Status Register
D6.54 TRCPIDR0, ETM Peripheral Identification Register 0
D6.55 TRCPIDR1, ETM Peripheral Identification Register 1
D6.56 TRCPIDR2, ETM Peripheral Identification Register 2
D6.57 TRCPIDR3, ETM Peripheral Identification Register 3
D6.58 TRCPIDR4, ETM Peripheral Identification Register 4
D6.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7
D6.60 TRCPRGCTLR, Programming Control Register
D6.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
D6.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
D6.63 TRCSEQRSTEVR, Sequencer Reset Control Register
D6.64 TRCSEQSTR, Sequencer State Register
D6.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
D6.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
D6.67 TRCSTALLCTLR, Stall Control Register
D6.68 TRCSTATR, Status Register
D6.69 TRCSYNCPR, Synchronization Period Register
D6.70 TRCTRACEIDR, Trace ID Register
D6.71 TRCTSCTLR, Global Timestamp Control Register
D6.72 TRCVICTLR, ViewInst Main Control Register
D6.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
D6.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
D6.75 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0
D6.76 TRCVMIDCVR0, VMID Comparator Value Register 0
Part E Appendices
A Revisions
A.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-02 31 January 2018 Confidential First release for r0p0
0100-00 06 July 2018 Confidential First release for r1p0
0101-00 21 February 2019 Non-Confidential First release for r1p1

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