ARM® Cortex®-A55 Core Technical Reference Manual

Revision r1p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographic conventions
Timing diagrams
Signals
Additional reading
Feedback
Feedback on this product
Feedback on content
Part A Functional description
A1 Introduction
A1.1 About the core
A1.2 Features
A1.3 Implementation options
A1.4 Supported standards and specifications
A1.5 Test features
A1.6 Design tasks
A1.7 Product revisions
A2 Technical overview
A2.1 Components
A2.2 Interfaces
A2.3 About system control
A2.4 About the Generic Timer
A3 Clocks, resets, and input synchronization
A3.1 About Clocks, Resets, and Input Synchronization
A3.2 Asynchronous interface
A4 Power management
A4.1 About power management
A4.2 Voltage domains
A4.3 Power domains
A4.4 Architectural clock gating modes
A4.4.1 Core Wait for Interrupt
A4.4.2 Core Wait for Event
A4.5 Power control
A4.6 Power modes
A4.6.1 On
A4.6.2 Off
A4.6.3 Off (emulated)
A4.6.4 SIMD dynamic retention
A4.6.5 Core dynamic retention
A4.6.6 Debug Recovery Mode
A4.7 Encoding for power modes
A4.8 Power down sequence
A4.9 Debug over powerdown
A5 Memory Management Unit
A5.1 About the MMU
A5.1.1 Main functions
A5.1.2 AAarch32 and AArch64 behavior differences
A5.2 TLB organization
A5.2.1 L1 TLB
A5.2.2 L2 TLB
A5.2.3 IPA cache RAM
A5.2.4 Walk cache RAM
A5.3 TLB match process
A5.4 Translation table walks
A5.4.1 AArch64 behavior
A5.4.2 AArch32 behavior
A5.5 MMU memory accesses
A5.5.1 Configuring MMU accesses
A5.5.2 Hardware management of the Access flag and dirty state
A5.6 Responses
A5.6.1 MMU responses
A5.6.2 MMU aborts
A5.6.3 External aborts
A5.6.4 Mis-programming contiguous hints
A5.6.5 Conflict aborts
A5.6.6 Memory Behavior
A5.6.7 Support for ARMv8 device memory types
A6 Level 1 memory system
A6.1 About the L1 memory system
A6.2 Cache behavior
A6.2.1 Instruction cache disabled behavior
A6.2.2 Instruction cache speculative memory accesses
A6.2.3 Data cache disabled behavior
A6.2.4 Data cache maintenance considerations
A6.2.5 Data cache coherency
A6.2.6 Write Streaming Mode
A6.2.7 Data cache invalidate on reset
A6.3 L1 instruction memory system
A6.3.1 Program flow prediction
A6.4 L1 data memory system
A6.4.1 Memory system implementation
A6.4.2 Internal exclusive monitor
A6.4.3 Exclusive monitor
A6.5 Data prefetching
A6.6 Direct access to internal memory
A6.6.1 Encoding for tag and data in the L1 data cache
A6.6.2 Encoding for tag and data in the L1 instruction cache
A6.6.3 Encoding for the L2 TLB
A6.6.4 Main TLB RAM descriptor fields
A6.6.5 Walk cache descriptor fields
A6.6.6 IPA cache descriptor fields
A7 Level 2 memory system
A7.1 About the L2 memory system
A7.2 Optional integrated L2 cache
A7.3 Support for memory types
A8 Reliability, Availability, and Serviceability (RAS)
A8.1 Cache ECC and parity
A8.2 Cache protection behavior
A8.3 Uncorrected errors and data poisoning
A8.4 RAS error types
A8.5 Error synchronization barrier
A8.6 Error reporting
A8.7 Error injection
A9 Generic Interrupt Controller CPU interface
A9.1 About the Generic Interrupt Controller CPU Interface
A9.2 Bypassing the CPU Interface
Part B Register Descriptions
B1 AArch32 system registers
B1.1 AArch32 registers
B1.2 AArch32 architectural system register summary
B1.3 AArch32 implementation defined register summary
B1.4 AArch32 registers by functional group
B1.5 ACTLR, Auxiliary Control Register
B1.6 ACTLR2, Auxiliary Control Register 2
B1.7 ADFSR, Auxiliary Data Fault Status Register
B1.8 AIDR, Auxiliary ID Register
B1.9 AIFSR, Auxiliary Instruction Fault Status Register
B1.10 AMAIR0, Auxiliary Memory Attribute Indirection Register 0
B1.11 AMAIR1, Auxiliary Memory Attribute Indirection Register 1
B1.12 CCSIDR, Cache Size ID Register
B1.13 CLIDR, Cache Level ID Register
B1.14 CPACR, Architectural Feature Access Control Register
B1.15 CPUACTLR, CPU Auxiliary Control Register
B1.16 CPUCFR, CPU Configuration Register
B1.17 CPUECTLR, CPU Extended Control Register
B1.18 CPUPCR, CPU Private Control Register
B1.19 CPUPMR, CPU Private Mask Register
B1.20 CPUPOR, CPU Private Operation Register
B1.21 CPUPSELR, CPU Private Selection Register
B1.22 CPUPWRCTLR, CPU Power Control Register
B1.23 CSSELR, Cache Size Selection Register
B1.24 CTR, Cache Type Register
B1.25 DFSR, Data Fault Status Register
B1.25.1 DFSR with Short-descriptor translation table format
B1.25.2 DFSR with Long-descriptor translation table format
B1.26 DISR, Deferred Interrupt Status Register
B1.26.1 DISR with Short-descriptor translation table format
B1.26.2 DISR with Long-descriptor translation table format
B1.26.3 DISR at EL2
B1.27 ERRIDR, Error ID Register
B1.28 ERRSELR, Error Record Select Register
B1.29 ERXADDR, Selected Error Record Address Register
B1.30 ERXADDR2, Selected Error Record Address Register 2
B1.31 ERXCTLR, Selected Error Record Control Register
B1.32 ERXCTLR2, Selected Error Record Control Register 2
B1.33 ERXFR, Selected Error Record Feature Register
B1.34 ERXFR2, Selected Error Record Feature Register 2
B1.35 ERXMISC0, Selected Error Miscellaneous Register 0
B1.36 ERXMISC1, Selected Error Miscellaneous Register 1
B1.37 ERXMISC2, Selected Error Record Miscellaneous Register 2
B1.38 ERXMISC3, Selected Error Record Miscellaneous Register 3
B1.39 ERXPFGCDNR, Selected Error Pseudo Fault Generation Count Down Register
B1.40 ERXPFGCTLR, Selected Error Pseudo Fault Generation Control Register
B1.41 ERXPFGFR, Selected Pseudo Fault Generation Feature Register
B1.42 ERXSTATUS, Selected Error Record Primary Status Register
B1.43 FCSEIDR, FCSE Process ID Register
B1.44 HACR, Hyp Auxiliary Configuration Register
B1.45 HACTLR, Hyp Auxiliary Control Register
B1.46 HACTLR2, Hyp Auxiliary Control Register 2
B1.47 HADFSR, Hyp Auxiliary Data Fault Status Syndrome Register
B1.48 HAIFSR, Hyp Auxiliary Instruction Fault Status Syndrome Register
B1.49 HAMAIR0, Hyp Auxiliary Memory Attribute Indirection Register 0
B1.50 HAMAIR1, Hyp Auxiliary Memory Attribute Indirection Register 1
B1.51 HCR, Hyp Configuration Register
B1.52 HCR2, Hyp Configuration Register 2
B1.53 HSCTLR, Hyp System Control Register
B1.54 HSR, Hyp Syndrome Register
B1.54.1 Encoding of ISS[24:20] when HSR[31:30] is 0b00
B1.55 HTTBR, Hyp Translation Table Base Register
B1.56 ID_AFR0, Auxiliary Feature Register 0
B1.57 ID_DFR0, Debug Feature Register 0
B1.58 ID_ISAR0, Instruction Set Attribute Register 0
B1.59 ID_ISAR1, Instruction Set Attribute Register 1
B1.60 ID_ISAR2, Instruction Set Attribute Register 2
B1.61 ID_ISAR3, Instruction Set Attribute Register 3
B1.62 ID_ISAR4, Instruction Set Attribute Register 4
B1.63 ID_ISAR5, Instruction Set Attribute Register 5
B1.64 ID_ISAR6, Instruction Set Attribute Register 6
B1.65 ID_MMFR0, Memory Model Feature Register 0
B1.66 ID_MMFR1, Memory Model Feature Register 1
B1.67 ID_MMFR2, Memory Model Feature Register 2
B1.68 ID_MMFR3, Memory Model Feature Register 3
B1.69 ID_MMFR4, Memory Model Feature Register 4
B1.70 ID_PFR0, Processor Feature Register 0
B1.71 ID_PFR1, Processor Feature Register 1
B1.72 IFSR, Instruction Fault Status Register
B1.72.1 IFSR with Short-descriptor translation table format
B1.72.2 IFSR with Long-descriptor translation table format
B1.73 MIDR, Main ID Register
B1.74 MPIDR, Multiprocessor Affinity Register
B1.75 PAR, Physical Address Register
B1.75.1 PAR with Short-descriptor translation table format
B1.75.2 PAR with Long-descriptor translation table format
B1.76 REVIDR, Revision ID Register
B1.77 SCR, Secure Configuration Register
B1.78 SCTLR, System Control Register
B1.79 SDCR, Secure Debug Control Register
B1.80 TTBCR, Translation Table Base Control Register
B1.80.1 TTBCR with Short-descriptor translation table format
B1.80.2 TTBCR with Long-descriptor translation table format
B1.81 TTBCR2, Translation Table Base Control Register 2
B1.82 TTBR0, Translation Table Base Register 0
B1.82.1 TTBR0 with Short-descriptor translation table format
B1.82.2 TTBR0 with Long-descriptor translation table format
B1.83 TTBR1, Translation Table Base Register 1
B1.83.1 TTBR1 with Short-descriptor translation table format
B1.83.2 TTBR1 with Long-descriptor translation table format
B1.84 VDFSR, Virtual SError Exception Syndrome Register
B1.85 VDISR, Virtual Deferred Interrupt Status Register
B1.85.1 VDISR with Short-descriptor translation table format
B1.85.2 VDISR with Long-descriptor translation table format
B1.86 VMPIDR, Virtualization Multiprocessor ID Register
B1.87 VPIDR, Virtualization Processor ID Register
B1.88 VTCR, Virtualization Translation Control Register
B1.89 VTTBR, Virtualization Translation Table Base Register
B2 AArch64 system registers
B2.1 AArch64 registers
B2.2 AArch64 architectural system register summary
B2.3 AArch64 implementation defined register summary
B2.4 AArch64 registers by functional group
B2.5 ACTLR_EL1, Auxiliary Control Register, EL1
B2.6 ACTLR_EL2, Auxiliary Control Register, EL2
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1
B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2
B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3
B2.14 AIDR_EL1, Auxiliary ID Register, EL1
B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1
B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2
B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
B2.19 CLIDR_EL1, Cache Level ID Register, EL1
B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1
B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2
B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3
B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1
B2.24 CPUCFR_EL1, CPU Configuration Register, EL1
B2.25 CPUECTLR_EL1, CPU Extended Control Register, EL1
B2.26 CPUPCR_EL3, CPU Private Control Register, EL3
B2.27 CPUPMR_EL3, CPU Private Mask Register, EL3
B2.28 CPUPOR_EL3, CPU Private Operation Register, EL3
B2.29 CPUPSELR_EL3, CPU Private Selection Register, EL3
B2.30 CPUPWRCTLR_EL1, Power Control Register, EL1
B2.31 CSSELR_EL1, Cache Size Selection Register, EL1
B2.32 CTR_EL0, Cache Type Register, EL0
B2.33 DCZID_EL0, Data Cache Zero ID Register, EL0
B2.34 DISR_EL1, Deferred Interrupt Status Register, EL1
B2.35 ERRIDR_EL1, Error ID Register, EL1
B2.36 ERRSELR_EL1, Error Record Select Register, EL1
B2.37 ERXADDR_EL1, Selected Error Record Address Register, EL1
B2.38 ERXCTLR_EL1, Selected Error Record Control Register, EL1
B2.39 ERXFR_EL1, Selected Error Record Feature Register, EL1
B2.40 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
B2.41 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1
B2.42 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
B2.43 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
B2.44 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1
B2.45 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
B2.46 ESR_EL1, Exception Syndrome Register, EL1
B2.47 ESR_EL2, Exception Syndrome Register, EL2
B2.48 ESR_EL3, Exception Syndrome Register, EL3
B2.49 HACR_EL2, Hyp Auxiliary Configuration Register, EL2
B2.50 HCR_EL2, Hypervisor Configuration Register, EL2
B2.51 HPFAR_EL2, Hypervisor IPA Fault Address Register, EL2
B2.52 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1
B2.53 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
B2.54 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
B2.55 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1
B2.56 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1
B2.57 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
B2.58 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
B2.59 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1
B2.60 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
B2.61 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1
B2.62 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1
B2.63 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1
B2.64 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
B2.65 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
B2.66 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1
B2.67 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1
B2.68 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
B2.69 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1
B2.70 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
B2.71 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1
B2.72 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1
B2.73 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
B2.74 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1
B2.75 IFSR32_EL2, Instruction Fault Status Register, EL2
B2.75.1 IFSR32_EL2 with Short-descriptor translation table format
B2.75.2 IFSR32_EL2 with Long-descriptor translation table format
B2.76 LORC_EL1, LORegion Control Register, EL1
B2.77 LOREA_EL1, LORegion End Address Register, EL1
B2.78 LORID_EL1, Limited Order Region Identification Register, EL1
B2.79 LORN_EL1, LORegion Number Register, EL1
B2.80 LORSA_EL1, LORegion Start Address Register, EL1
B2.81 MDCR_EL3, Monitor Debug Configuration Register, EL3
B2.82 MIDR_EL1, Main ID Register, EL1
B2.83 MPIDR_EL1, Multiprocessor Affinity Register, EL1
B2.84 PAR_EL1, Physical Address Register, EL1
B2.85 REVIDR_EL1, Revision ID Register, EL1
B2.86 RVBAR_EL3, Reset Vector Base Address Register, EL3
B2.87 SCTLR_EL1, System Control Register, EL1
B2.88 SCTLR_EL2, System Control Register, EL2
B2.89 SCTLR_EL3, System Control Register, EL3
B2.90 TCR_EL1, Translation Control Register, EL1
B2.91 TCR_EL2, Translation Control Register, EL2
B2.92 TCR_EL3, Translation Control Register, EL3
B2.93 TTBR0_EL1, Translation Table Base Register 0, EL1
B2.94 TTBR0_EL2, Translation Table Base Register 0, EL2
B2.95 TTBR0_EL3, Translation Table Base Register 0, EL3
B2.96 TTBR1_EL1, Translation Table Base Register 1, EL1
B2.97 TTBR1_EL2, Translation Table Base Register 1, EL2
B2.98 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2
B2.98.1 VDISR_EL2 with long-descriptor translation table format
B2.98.2 VDISR_EL2 with short-descriptor translation table format
B2.98.3 VDISR_EL2 at EL1 using AArch64
B2.99 VMPIDR_EL2, Virtualization Multiprocessor ID Register, EL2
B2.100 VPIDR_EL2, Virtualization Processor ID Register, EL2
B2.101 VSESR_EL2, Virtual SError Exception Syndrome Register
B2.102 VTCR_EL2, Virtualization Translation Control Register, EL2
B2.103 VTTBR_EL2, Virtualization Translation Table Base Register, EL2
B3 Error system registers
B3.1 Error system register summary
B3.2 ERR0ADDR, Error Record Address Register
B3.3 ERR0CTLR, Error Record Control Register
B3.4 ERR0FR, Error Record Feature Register
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0
B3.6 ERR0MISC1, Error Record Miscellaneous Register 1
B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register
B3.10 ERR0STATUS, Error Record Primary Status Register
B4 GIC registers
B4.1 CPU interface registers
B4.2 AArch32 physical GIC CPU interface system register summary
B4.3 ICC_AP0R0, Interrupt Controller Active Priorities Group 0 Register 0
B4.4 ICC_AP1R0, Interrupt Controller Active Priorities Group 1 Register 0
B4.5 ICC_BPR0, Interrupt Controller Binary Point Register 0
B4.6 ICC_BPR1, Interrupt Controller Binary Point Register 1
B4.7 ICC_CTLR, Interrupt Controller Control Register
B4.8 ICC_HSRE, Interrupt Controller Hyp System Register Enable Register
B4.9 ICC_MCTLR, Interrupt Controller Monitor Control Register
B4.10 ICC_MSRE, Interrupt Controller Monitor System Register Enable Register
B4.11 ICC_SRE, Interrupt Controller System Register Enable Register
B4.12 AArch32 virtual GIC CPU interface register summary
B4.13 ICV_AP0R0, Interrupt Controller Virtual Active Priorities Group 0 Register 0
B4.14 ICV_AP1R0, Interrupt Controller Virtual Active Priorities Group 1 Register 0
B4.15 ICV_BPR0, Interrupt Controller Virtual Binary Point Register 0
B4.16 ICV_BPR1, Interrupt Controller Virtual Binary Point Register 1
B4.17 ICV_CTLR, Interrupt Controller Virtual Control Register
B4.18 AArch32 virtual interface control system register summary
B4.19 ICH_AP0R0, Interrupt Controller Hyp Active Priorities Group 0 Register 0
B4.20 ICH_AP1R0, Interrupt Controller Hyp Active Priorities Group 1 Register 0
B4.21 ICH_HCR, Interrupt Controller Hyp Control Register
B4.22 ICH_VMCR, Interrupt Controller Virtual Machine Control Register
B4.23 ICH_VTR, Interrupt Controller VGIC Type Register
B4.24 AArch64 physical GIC CPU interface system register summary
B4.25 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1
B4.26 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1
B4.27 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1
B4.28 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1
B4.29 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
B4.30 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
B4.31 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
B4.32 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2
B4.33 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
B4.34 AArch64 virtual GIC CPU interface register summary
B4.35 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0, EL1
B4.36 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0, EL1
B4.37 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1
B4.38 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1
B4.39 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1
B4.40 AArch64 virtual interface control system register summary
B4.41 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2
B4.42 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2
B4.43 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
B4.44 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2
B4.45 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
Part C Debug descriptions
C1 Debug
C1.1 About debug methods
C1.2 Debug functional description
C1.3 Debug register interfaces
C1.3.1 Core interfaces
C1.3.2 Effects of resets on debug registers
C1.3.3 External access permissions to debug registers
C1.4 Debug events
C1.4.1 Watchpoint debug events
C1.4.2 Debug OS Lock
C1.5 External debug interface
C2 PMU
C2.1 About the PMU
C2.2 PMU functional description
C2.3 External register access permissions to the PMU registers
C2.4 PMU events
C2.5 PMU interrupts
C2.6 Exporting PMU events
C3 ETM
C3.1 About the ETM
C3.2 ETM trace unit generation options and resources
C3.3 ETM trace unit functional description
C3.4 Resetting the ETM
C3.5 Programming and reading ETM trace unit registers
C3.6 ETM trace unit register interfaces
C3.7 Interaction with the PMU and Debug
Part D Debug registers
D1 AArch32 Debug Registers
D1.1 AArch32 debug register summary
D1.2 DBGBCR, Debug Breakpoint Control Registers
D1.3 DBGDEVID, Debug Device ID Register
D1.4 DBGDEVID1, Debug Device ID Register 1
D1.5 DBGDIDR, Debug ID Register
D1.6 DBGWCR, Debug Watchpoint Control Registers
D2 AArch64 debug registers
D2.1 AArch64 debug register summary
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
D2.5 MDSCR_EL1, Monitor Debug System Control Register, EL1
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
D3.2 EDCIDR0, External Debug Component Identification Register 0
D3.3 EDCIDR1, External Debug Component Identification Register 1
D3.4 EDCIDR2, External Debug Component Identification Register 2
D3.5 EDCIDR3, External Debug Component Identification Register 3
D3.6 EDDEVID, External Debug Device ID Register 0
D3.7 EDDEVID1, External Debug Device ID Register 1
D3.8 EDDFR, External Debug Feature Register
D3.9 EDITCTRL, External Debug Integration Mode Control Register
D3.10 EDPFR, External Debug Processor Feature Register
D3.11 EDPIDR0, External Debug Peripheral Identification Register 0
D3.12 EDPIDR1, External Debug Peripheral Identification Register 1
D3.13 EDPIDR2, External Debug Peripheral Identification Register 2
D3.14 EDPIDR3, External Debug Peripheral Identification Register 3
D3.15 EDPIDR4, External Debug Peripheral Identification Register 4
D3.16 EDPIDRn, External Debug Peripheral Identification Registers 5-7
D3.17 EDRCR, External Debug Reserve Control Register
D4 AArch32 PMU Registers
D4.1 AArch32 PMU register summary
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0
D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1
D4.4 PMCR, Performance Monitors Control Register
D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
D6.2 PMCFGR, Performance Monitors Configuration Register
D6.3 PMCIDR0, Performance Monitors Component Identification Register 0
D6.4 PMCIDR1, Performance Monitors Component Identification Register 1
D6.5 PMCIDR2, Performance Monitors Component Identification Register 2
D6.6 PMCIDR3, Performance Monitors Component Identification Register 3
D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0
D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1
D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2
D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3
D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4
D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7
D7 PMU snapshot registers
D7.1 PMU snapshot register summary
D7.2 PMPCSSR, Snapshot Program Counter Sample Register
D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register
D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register
D7.5 PMSSSR, PMU Snapshot Status Register
D7.6 PMOVSSR, PMU Overflow Status Snapshot Register
D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register
D7.8 PMEVCNTSR 0-5, PMU Cycle Counter Snapshot Registers
D7.9 PMSSCR, PMU Snapshot Capture Register
D8 ETM registers
D8.1 ETM register summary
D8.2 TRCACATRn, Address Comparator Access Type Registers 0-7
D8.3 TRCACVRn, Address Comparator Value Registers 0-7
D8.4 TRCAUTHSTATUS, Authentication Status Register
D8.5 TRCAUXCTLR, Auxiliary Control Register
D8.6 TRCBBCTLR, Branch Broadcast Control Register
D8.7 TRCCCCTLR, Cycle Count Control Register
D8.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
D8.9 TRCCIDCVR0, Context ID Comparator Value Register 0
D8.10 TRCCIDR0, ETM Component Identification Register 0
D8.11 TRCCIDR1, ETM Component Identification Register 1
D8.12 TRCCIDR2, ETM Component Identification Register 2
D8.13 TRCCIDR3, ETM Component Identification Register 3
D8.14 TRCCLAIMCLR, Claim Tag Clear Register
D8.15 TRCCLAIMSET, Claim Tag Set Register
D8.16 TRCCNTCTLR0, Counter Control Register 0
D8.17 TRCCNTCTLR1, Counter Control Register 1
D8.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
D8.19 TRCCNTVRn, Counter Value Registers 0-1
D8.20 TRCCONFIGR, Trace Configuration Register
D8.21 TRCDEVAFF0, Device Affinity Register 0
D8.22 TRCDEVAFF1, Device Affinity Register 1
D8.23 TRCDEVARCH, Device Architecture Register
D8.24 TRCDEVID, Device ID Register
D8.25 TRCDEVTYPE, Device Type Register
D8.26 TRCEVENTCTL0R, Event Control 0 Register
D8.27 TRCEVENTCL1R, Event Control 1 Register
D8.28 TRCEXTINSELR, External Input Select Register
D8.29 TRCIDR0, ID Register 0
D8.30 TRCIDR1, ID Register 1
D8.31 TRCIDR2, ID Register 2
D8.32 TRCIDR3, ID Register 3
D8.33 TRCIDR4, ID Register 4
D8.34 TRCIDR5, ID Register 5
D8.35 TRCIDR8, ID Register 8
D8.36 TRCIDR9, ID Register 9
D8.37 TRCIDR10, ID Register 10
D8.38 TRCIDR11, ID Register 11
D8.39 TRCIDR12, ID Register 12
D8.40 TRCIDR13, ID Register 13
D8.41 TRCIMSPEC0, Implementation Specific Register 0
D8.42 TRCITATBIDR, Integration ATB Identification Register
D8.43 TRCITCTRL, Integration Mode Control Register
D8.44 TRCITIATBINR, Integration Instruction ATB In Register
D8.45 TRCITIATBOUTR, Integration Instruction ATB Out Register
D8.46 TRCITIDATAR, Integration Instruction ATB Data Register
D8.47 TRCLAR, Software Lock Access Register
D8.48 TRCLSR, Software Lock Status Register
D8.49 TRCCNTVRn, Counter Value Registers 0-1
D8.50 TRCOSLAR, OS Lock Access Register
D8.51 TRCOSLSR, OS Lock Status Register
D8.52 TRCPDCR, Power Down Control Register
D8.53 TRCPDSR, Power Down Status Register
D8.54 TRCPIDR0, ETM Peripheral Identification Register 0
D8.55 TRCPIDR1, ETM Peripheral Identification Register 1
D8.56 TRCPIDR2, ETM Peripheral Identification Register 2
D8.57 TRCPIDR3, ETM Peripheral Identification Register 3
D8.58 TRCPIDR4, ETM Peripheral Identification Register 4
D8.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7
D8.60 TRCPRGCTLR, Programming Control Register
D8.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
D8.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
D8.63 TRCSEQRSTEVR, Sequencer Reset Control Register
D8.64 TRCSEQSTR, Sequencer State Register
D8.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
D8.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
D8.67 TRCSTALLCTLR, Stall Control Register
D8.68 TRCSTATR, Status Register
D8.69 TRCSYNCPR, Synchronization Period Register
D8.70 TRCTRACEIDR, Trace ID Register
D8.71 TRCTSCTLR, Global Timestamp Control Register
D8.72 TRCVICTLR, ViewInst Main Control Register
D8.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
D8.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
D8.75 TRCVMIDCVR0, VMID Comparator Value Register 0
Part E Appendices
A AArch32 UNPREDICTABLE Behaviors
A.1 Use of R15 by Instruction
A.2 UNPREDICTABLE instructions within an IT Block
A.3 Load/Store accesses crossing page boundaries
A.4 ARMv8 Debug UNPREDICTABLE behaviors
A.5 Other unpredictable behaviors
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 30 September 2016 Confidential First release for r0p0
0001-00 16 December 2016 Confidential First release for r0p1
0100-00 23 June 2017 Non-Confidential First release for r1p0

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